Flash memory storage apparatus

• US 10,445,011 B2
• Filed: 01/15/2018
• Issued: 10/15/2019
• Est. Priority Date: 05/19/2017
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chen, Chung-Zen
• Primary Examiner(s): Farrokh, Hashem
• Application Number:
  US15/871,124
• Publication Number:
  US 20180335970A1
• Time in Patent Office: 638 Days
• Field of Search: 711103
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.

Claims

1. A flash memory storage apparatus having a plurality of operation modes, the flash memory storage apparatus comprising:

a memory controller circuit configured to control the flash memory storage apparatus to operate in one of the plurality of operation modes, wherein the plurality of operation modes comprise a low standby current mode; and

a memory cell array coupled to the memory controller circuit and configured to store data that comprises read-only memory data,

wherein the memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command, and wakes up the flash memory storage apparatus from the low standby current mode according to a second command,

wherein when the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept,

wherein the plurality of operation modes comprise a normal standby mode and a deep power down mode; and

the flash memory storage apparatus needs a first wake-up time, a second wake-up time, and a third wake-up time to be woken up from the low standby current mode, the normal standby mode, and the deep power down mode respectively, wherein the first wake-up time is longer than the second wake-up time and shorter than the third wake-up time.

2. The flash memory storage apparatus as recited in claim 1, wherein the plurality of operation modes has a first current, a second current, and a third current when operating in the low standby current mode, the normal standby mode, and the deep power down mode respectively, wherein the first current is smaller than the second current and greater than the third current.

3. The flash memory storage apparatus as recited in claim 1, further comprising:

a word line decoder circuit coupled to a plurality of word lines of the flash memory storage apparatus; and

a voltage generator circuit coupled to the word line decoder circuit and configured to provide a high voltage to the word line decoder circuit through a node,

wherein in the low standby current mode, a plurality of transistor switches in the voltage generator circuit are not turned on according to a control signal.

4. The flash memory storage apparatus as recited in claim 3, wherein the voltage generator circuit comprises a clock generator, a reference voltage generator, and a voltage regulator;

and the reference voltage generator is coupled to a first voltage by a first transistor switch, the voltage regulator is coupled to a second voltage by a second transistor switch, and the clock generator comprises a third transistor switch, wherein in the low standby current mode, the first transistor switch, the second transistor switch and the third transistor switch are not turned on according to the control signal.

5. The flash memory storage apparatus as recited in claim 4, wherein the node is coupled to the second voltage by a fourth transistor switch;

and in the low standby current mode, the fourth transistor switch is turned on according to the control signal so as to change a voltage of the node to the second voltage.

6. The flash memory storage apparatus as recited in claim 3, wherein in the low standby current mode, the node is floating.

7. A flash memory storage apparatus having a plurality of operation modes, the flash memory storage apparatus comprising:

a memory controller circuit configured to control the flash memory storage apparatus to operate in one of the plurality of operation modes, wherein the plurality of operation modes comprises a low standby current mode; and

a memory cell array coupled to the memory controller circuit and configured to store data that comprises read-only memory data,

wherein the memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command, and wakes up the flash memory storage apparatus from the low standby current mode according to a second command,

wherein the plurality of operation modes comprise a normal standby mode and a deep power down mode; and

the flash memory storage apparatus needs a first wake-up time, a second wake-up time, and a third wake-up time to be woken up from the low standby current mode, the normal standby mode, and the deep power down mode respectively, wherein the first wake-up time is longer than the second wake-up time and shorter than the third wake-up time.

8. The flash memory storage apparatus as recited in claim 7, further comprising:

a word line decoder circuit coupled to a plurality of word lines of the flash memory storage apparatus; and

a voltage generator circuit coupled to the word line decoder circuit and configured to provide a high voltage to the word line decoder circuit through a node,

wherein in the low standby current mode, a plurality of transistor switches in the voltage generator circuit are not turned on according to a control signal.

9. The flash memory storage apparatus as recited in claim 8, wherein the voltage generator circuit comprises a clock generator, a reference voltage generator, and a voltage regulator;

and the reference voltage generator is coupled to a first voltage by a first transistor switch, the voltage regulator is coupled to a second voltage by a second transistor switch, and the clock generator comprises a third transistor switch, wherein in the low standby current mode, the first transistor switch, the second transistor switch and the third transistor switch are not turned on according to the control signal.

10. The flash memory storage apparatus as recited in claim 7, wherein the plurality of operation modes has a first current, a second current, and a third current when operating in the low standby current mode, the normal standby mode, and the deep power down mode respectively, wherein the first current is smaller than the second current and greater than the third current.