Methods of operating a computing system including a host processing data of first size and a storage device processing data of second size and including a memory controller and a non-volatile memory

• US 10,445,014 B2
• Filed: 08/14/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/20/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Hee Hyun, Kim, Young Sik, Kim, Jin Woo, Park, Young Jo, Park, Jae Geun, Cho, Young Jin
• Primary Examiner(s): Kim, Hong C
• Application Number:
  US15/676,651
• Publication Number:
  US 20180081584A1
• Time in Patent Office: 792 Days
• Field of Search: 711118, 711103, 711 4, 710 36, 710 52
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

Claims

1. A method of operating a memory controller in a storage device including a non-volatile memory (NVM), wherein the memory controller comprises a memory processor a buffer, and a buffer control circuit, the method comprising:

using the memory processor to receive a block of data from a host, store the block of data in the buffer, and thereafter program the block of data in the NVM if the received block of data has a size at least as equal to a second size; and

using the memory processor to;

sequentially receive first data segments from the host, wherein each first date segment has a first size;

sequentially store the received first data segments in the buffer until a cumulative size of the received first data segments reaches the second size; and

then,

program the sequentially stored first data segments in the NVM,

wherein the first size corresponds to a unit size for data processed by the host and the second size is an integer multiple of the first size and corresponds to a unit size of data programmed in the NVM,

the buffer control circuit determines the cumulative size of the received first data segments and generates storage information corresponding to the received first data segments, and provides the storage information to the memory processor, and

the memory processor generate a buffer indication signal in response to the storage information that causes the first data segments sequentially stored in the buffer to be programmed in the NVM when the cumulative size of the received first data segments reaches the second size.

2. The method of claim 1, wherein data stored in the buffer is arranged according to a buffer address data structure (buffer address) including a plurality of buffer address elements and a non-volatile memory address data structure (NVM address) including a plurality of NVM address elements,

the received first data segments are respectively stored in a buffer address element selected from among the plurality of buffer address elements, and

each buffer address element comprises a plurality of sub-buffer addresses respectively used to store one of the received first data segments.

3. The method of claim 2, further comprising:

generating a buffer-to-NVM address mapping table in the host, wherein the buffer-to-NVM address table maps each one of the buffer address elements to a corresponding one of the NVM address elements.

4. The method of claim 3, further comprising:

receiving the buffer-to-NVM mapping table in the storage device from the host during a storage device initialization procedure.

5. The method of claim 1, wherein during an initialization of the storage device the method further comprises:

transmitting initialization information to the host, wherein the initialization information includes the buffer-to-NVM mapping table.

6. The method of claim 5, further comprising at least one of:

updating a copy of the buffer-to-NVM mapping table stored in the storage device using the memory controller; and

initialing an updating of a copy the buffer-to-NVM mapping table stored in the host using the memory controller, changed one-to-one mapping information to the host.

7. The method of claim 6, wherein the non-volatile memory includes three-dimensional memory cells.

8. A method of operating a computing system including a host and a storage device including a memory controller including a buffer, and a non-volatile memory (NVM), the method comprising:

generating program data in the host to be programmed to the NVM;

if the program data has a size at least equal to a second size, performing a data block output operation using a device driver provided by the host to transmit a data block of the program data to the storage device, and thereafter programming the data block in the NVM;

if the program data has a size less than the second size, sequentially transmitting first data segments from the host to the storage device without use of the device driver, wherein each first data segment has a first size less than the second size,

sequentially and temporarily storing the first data segments in the buffer until a cumulative size of the stored first data segments equals or exceeds the second size, and

programming a second data segment having the second size and including the sequentially and temporarily stored the first data segments,

wherein the first size corresponds to a processing unit for data received by the storage device from the host or data temporarily stored by the host before transmitting of the first data segments to the storage device, and the second size is a processing unit for data programmed in the non-volatile memory.

9. The method of claim 8, wherein data stored in the buffer is arranged according to a buffer address data structure (buffer address) including a plurality of buffer address elements and a non-volatile memory address data structure (NVM address) including a plurality of NVM address elements,

the received first data segments are stored in a buffer address element selected from among the plurality of buffer address elements, and

each buffer address element comprises a plurality of sub-buffer addresses respectively used to store one of the received first data segments.

10. The method of claim 9, further comprising:

generating a buffer-to-NVM address mapping table in the host, wherein the buffer-to-NVM address table maps each one of the buffer address elements to a corresponding one of the NVM address elements,

wherein the buffer-to-NVM mapping table is received from the host during a storage device initialization procedure.

11. A method of operating a computing system including a host and a storage device, wherein the storage device includes a memory controller, a buffer and a non-volatile memory (NVM), the method comprising:

generating program data in the host;

if the size of the program data is equal to the second size, transmitting the program data from the host to the storage device as a block of data, storing the block of data in the buffer, and then programming the block of data in the NVM under the control of the memory controller; and

if the size of the program data is less than the second size, sequentially transmitting the program data from the host to the storage device as a sequence of first data segments wherein each first data segment has a first size, and storing the first data segments in the buffer until a cumulative size of the stored first data segments equals or exceeds the second size and then programming the stored first data segments in the NVM under the control of the memory controller,

wherein the first size corresponds to a unit size for processing data in the host, and the second size corresponds to a unit size for programming date in the NVM.

12. The method of claim 11, wherein the memory controller comprises a memory controller and a buffer control circuit, the method further comprising:

generating storage information (SI) in the buffer control circuit indicating the cumulative size of the first data segments;

generating a buffer indication signal (BIS) in the memory processor in response to the SI, wherein the stored first data segments are programmed in the NVM in response to the BIS when the cumulative size of the stored first data segments at least equals the second size.

13. The method of claim 11, wherein the sequence of first data segment is stored in the buffer in accordance with a buffer address data structure (buffer address) including a plurality of buffer address elements and a non-volatile memory address data structure (NVM address) including a plurality of NVM address elements, such that each one of the first data segments is respectively stored in a buffer address element selected from among the plurality of buffer address elements, and each buffer address element comprises a plurality of sub-buffer addresses respectively used to store one of the received first data segments.

14. The method of claim 13, further comprising:

generating a buffer-to-NVM address mapping table in one of the host and the storage device, wherein the buffer-to-NVM address table maps each one of the buffer address elements to a corresponding one of the NVM address elements.

15. The method of claim 14, further comprising:

generating the buffer-to-NVM address mapping table in the host; and

transmitting the buffer-to-NVM address mapping table from the host to the storage device during a storage device initialization procedure.