Memory system and operating method thereof

• US 10,445,019 B2
• Filed: 05/23/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/02/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Yun, Ho-Jung, Chun, Dong-Yeob
• Primary Examiner(s): Blust, Jason W
• Application Number:
  US15/602,273
• Publication Number:
  US 20180067696A1
• Time in Patent Office: 875 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system includes: a memory device comprising a plurality of memory dies in which command operations corresponding to a plurality of commands received from a host are performed; and a controller suitable for issuing RS (Read Status) commands to memory dies included in a first memory die group among the memory dies, issuing the RS commands to memory dies included in a second memory die group, checking whether the command operations are performed in the memory dies, through responses to the RS commands, and resetting an issue period of the RS commands in response to a change of the memory dies to which the RS commands are issued.

Claims

1. A memory system comprising:

a memory device comprising a plurality of memory dies, each memory die being suitable for performing one or more corresponding command operations in response to a plurality of corresponding commands entered from a host operatively coupled to the memory system; and

a controller suitable for sequentially issuing first read status (RS) commands to each of the memory dies included in a first memory die group defined among the memory dies according to a reception order of read commands entered from the host, issuing second RS commands to each of the memory dies included in a second memory die group defined among the memory dies according to scheduling information regardless of the reception order, checking whether the command operations are completed in the memory dies of the first and second memory die groups through responses to the RS commands, and respectively resetting issue periods of the RS commands according to the completion of the command operations of the memory dies of the first and second memory die groups.

2. The memory system of claim 1,

wherein the controller issues the first and second RS commands to the memory dies of the first and second memory die groups at first and second periods, and

wherein the scheduling information includes operation times of the command operations in the memory dies included in the second memory die group and the issue periods.

3. The memory system of claim 2,

wherein the controller issues the first RS commands for a first memory die having a high priority among the memory dies included in the first memory die group, and

wherein the controller issues the first RS commands for a second memory die having a low priority among the memory dies included in the first memory die group after checking completion of the command operation of the first memory die.

4. The memory system of claim 2, wherein the controller issues the second RS commands to the memory dies included in the second memory die group according to the operation times of the command operations and the issue periods.

5. The memory system of claim 4, wherein the controller issues third RS commands for a first memory die having a first operation time and fourth RS commands for a second memory die having a second operation time, among the memory dies included in the second memory die group.

6. The memory system of claim 5,

wherein the controller compares a first issue period of the third RS commands with the second operation time, and compares a second issue period of the fourth RS commands with the first operation time, and

wherein the controller resets the first and second issue periods, and then issues the third and fourth RS commands according to a result of the comparison.

7. The memory system of claim 6,

wherein the controller issues the fourth RS commands when the first issue period exceeds the second operation time, and

wherein the controller issues the third RS commands when the second issue period exceeds the first operation time.

8. The memory system of claim 4, wherein the controller issues fifth RS commands for a third memory die having a greatest operation time among the memory dies included in the second memory die group whenever a predetermined number of the fifth RS commands are issued to the memory dies other than the third memory die.

9. The memory system of claim 2, wherein the controller issues the second RS commands at third and fourth periods when a current issue period of the RS command to be currently issued exceeds a predetermined maximum issue period or when an accumulative time length of total issue periods so far including the issue period of the RS command to be currently issued exceeds a predetermined maximum accumulative time length.

10. The memory system of claim 9,

wherein the first to fourth periods are determined according to a reference clock of the memory system,

wherein the first and second periods have periods that are increased by an amount of integer multiples of the reference clock, and

wherein the third and fourth periods have periods that are maintained to or decreased by an amount of integer multiples of the reference clock.

11. The memory system of claim 8,

wherein the controller comprises:

a scheduler suitable for determining when the first to fifth RS commands are delivered into the respective memory dies; and

an aging controller, engaged with the scheduler, suitable for controlling the issue of the fifth RS commands to the third memory die, and

wherein the scheduler comprises;

a register suitable for storing the reception order of the commands, the issue periods and the operation time; and

a scheduling unit suitable for issuing the first to fifth RS commands to the respective memory dies according to the reception order of the commands, the issue periods and the operation times.

12. An operating method of a memory system comprising a memory device having a plurality of memory dies, the operating method comprising:

receiving a plurality of commands from a host for the memory dies, respectively;

performing, by the respective memory dies, command operations in response to the commands;

sequentially issuing first read status (RS) commands to each of the memory dies included in a first memory die group according to a reception order of read commands entered from the host;

issuing second RS commands to each of the memory dies included in a second memory die group according to scheduling information regardless of the reception order;

checking whether the command operations are completed in the memory dies through responses to the RS commands; and

respectively resetting issue periods of the RS commands according to the completion of the command operations of the memory dies.

13. The operating method of claim 12, wherein the issuing of the RS commands comprises:

issuing the first RS commands to the memory dies included in the first memory die group according to the reception order at first and second periods; and

issuing the second RS commands to the memory dies included in the second memory die group according to the scheduling information including operation times of the command operations in the memory dies included in the second memory die group and the issue periods at the first and second periods.

14. The operating method of claim 13, wherein the issuing of the first RS commands comprises:

issuing the first RS commands for a first memory die having a high priority among the memory dies included in the first memory die group;

checking whether the command operation of the first memory die is completed; and

issuing the first RS commands for a second memory die having a low priority among the memory dies included in the first memory die group after checking the completion of the command operation of the first memory die.

15. The operating method of claim 13, wherein the issuing of the second RS commands comprises issuing third RS commands for a first memory die having a first operation time and fourth RS commands for a second memory die having a second operation time, among the memory dies included in the second memory die group.

16. The operating method of claim 15, wherein the issuing of the second RS commands further comprises:

comparing a first issue period of the third RS commands with the second operation time, and comparing a second issue period of the fourth RS commands with the first operation time; and

resetting the first and second issue periods, and then issues the third and fourth RS commands according to a result of the comparing.

17. The operating method of claim 16, wherein the issuing of the second RS commands further comprises:

issuing the fourth RS commands when the first issue period exceeds the second operation time; and

issuing the third RS commands when the second issue period exceeds the first operation time.

18. The operating method of claim 13, wherein the issuing of the second RS commands further comprises issuing fifth RS commands for a third memory die having a greatest operation time among the memory dies included in the second memory die group whenever a predetermined number of the fifth RS commands are issued to the memory dies other than the third memory die.

19. The operating method of claim 13, wherein the issuing of the second RS commands further comprises issuing the second RS commands at third and fourth periods when a current issue period of the RS command to be currently issued exceeds a predetermined maximum issue period or when an accumulative time length of total issue periods so far including the issue period of the RS command to be currently issued exceeds a predetermined maximum accumulative time length.

20. The operating method of claim 19,

wherein the first to fourth periods are determined according to a reference clock of the memory system,

wherein the first and second periods have periods that are increased by an amount of integer multiples of the reference clock, and

wherein the third and fourth periods have periods that are maintained to or decreased by an amount of integer multiples of the reference clock.