Configurable processor with in-package look-up table

• US 10,445,067 B2
• Filed: 11/28/2018
• Issued: 10/15/2019
• Est. Priority Date: 05/06/2016
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US16/203,599
• Publication Number:
  US 20190114138A1
• Time in Patent Office: 321 Days
• Field of Search: None
• CPC Class Codes: G06F 7/4988 by table look-up
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A configurable processor comprises a memory die and a logic die. The memory die comprises a programmable memory array for storing a look-up table (LUT) for a mathematical function, while the logic die comprises an arithmetic logic circuit (ALC) for performing at least an arithmetic operation on selected data from the LUT, wherein said mathematical function includes more operation than the arithmetic operations performable by the ALC. Complex mathematical functions can be implemented and configured.

Claims

1. A configurable processor including a plurality of configurable computing elements, each of said configurable computing elements comprising:

at least a programmable memory array on a memory level for storing at least a portion of a look-up table (LUT) for a mathematical function;

at least an arithmetic logic circuit (ALC) on a logic level for performing at least an arithmetic operation on selected data from said LUT, wherein said logic level is a different physical level than said memory level; and

means for communicatively coupling said programmable memory array and said ALC;

wherein said mathematical function includes more operations than arithmetic operations performable by said ALC.

2. The configurable processor according to claim 1, wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

3. The configurable processor according to claim 1, wherein said memory level is located on a memory die;

and, said logic level is located on a logic die;

said memory die and said logic die are vertically stacked.

4. The configurable processor according to claim 3, wherein said memory die and said logic die at least partially overlap.

5. The configurable processor according to claim 1, wherein said programmable memory array is a re-programmable memory array, whereby said configurable processor can be re-configured to realize different mathematical functions.

6. A configurable processor for implementing a mathematical function, comprising:

at least first and second programmable memory arrays on a memory level, wherein said first programmable memory array stores at least a first portion of a first look-up table (LUT) for a first mathematical function; and

, said second programmable memory array stores at least a second portion of a second LUT for a second mathematical function;

at least an arithmetic logic circuit (ALC) on a logic level for performing at least an arithmetic operation on selected data from said first or second LUT, wherein said logic level is a different physical level than said memory level; and

means for communicatively coupling said first or second programmable memory array with said ALC;

wherein said mathematical function is a combination of at least said first and second mathematical functions; and

, each of said first and second mathematical functions includes more operations than arithmetic operations performable by said ALC.

7. The configurable processor according to claim 6, wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

8. The configurable processor according to claim 6, wherein said memory level is located on a memory die;

and, said logic level is located on a logic die;

said memory die and said logic die are vertically stacked.

9. The configurable processor according to claim 8, wherein said memory die and said logic die at least partially overlap.

10. The configurable processor according to claim 6, wherein said first and second programmable memory arrays are re-programmable memory arrays, whereby said configurable processor can be re-configured to realize different mathematical functions.

11. A configurable computing array for implementing a mathematical function, comprising:

at least an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function in a logic library;

at least an array of configurable computing elements comprising at least a first programmable memory array, a second programmable memory array and an arithmetic logic circuit (ALC), wherein said first programmable memory array stores at least a first portion of a first look-up table (LUT) for a first mathematical function;

said second programmable memory array stores at least a second portion of a second LUT for a second mathematical function; and

, said ALC performs at least an arithmetic operation on selected data from said first or second LUT;

means for communicatively coupling said configurable logic elements and said configurable computing elements;

whereby said configurable computing array realizes said mathematical function by programming said configurable logic elements and said configurable computing elements, wherein said mathematical function is a combination of at least said first and second mathematical functions;

wherein each of said first and second mathematical functions includes more operations than arithmetic operations included in said logic library; and

, each of said first and second mathematical functions includes more operations than arithmetic operations performable by said ALC.

12. The configurable computing array according to claim 11, wherein said arithmetic operations included in said logic library consist of addition and subtraction.

13. The configurable computing array according to claim 11, wherein said arithmetic operations performable by said ALC consist of addition, subtraction and multiplication.

14. The configurable computing array according to claim 11, further comprising at least a plurality of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

15. The configurable computing array according to claim 11, wherein said programmable memory array is a re-programmable memory array, whereby said configurable computing array can be re-configured to realize different mathematical functions.

16. The configurable computing array according to claim 11, wherein said first and second programmable memory array are located on a memory level;

said configurable logic arrays are located on a logic level; and

, said memory level and said logic level are different physical levels.

17. The configurable computing array according to claim 16, wherein said memory level is located on a memory die;

said logic level is located on a logic die; and

, said memory die and said logic die are vertically stacked.

18. The configurable computing array according to claim 17, wherein said memory die and said logic die at least partially overlap.

19. The configurable computing array according to claim 17, wherein said ALC is formed on said logic die.

20. The configurable computing array according to claim 17, wherein said ALC is formed on another logic die.