Random number generator
First Claim
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1. A random number generation circuit, comprising:
- a first logic gate;
a second logic gate;
a first adjustable delay element assembly coupled in series between an output of the first logic gate and an input of the second logic gate;
a second adjustable delay element assembly coupled in series between an output of the second logic gate and an input of the first logic gate; and
a digitizing circuit coupled to an output of the second adjustable delay element, wherein the digitizing circuit comprises;
an asynchronous counter, wherein an input of the asynchronous counter is coupled to the output of the second adjustable delay element; and
a sampling circuit to sample an output of the asynchronous counter.
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Abstract
An integrated random signal generation circuit includes two logic gates, the output of each gate coupled to a respective first input of the other gate via assemblies of delay elements. The respective delays introduced by the assemblies of delay elements are adjustable.
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Citations
20 Claims
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1. A random number generation circuit, comprising:
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a first logic gate; a second logic gate; a first adjustable delay element assembly coupled in series between an output of the first logic gate and an input of the second logic gate; a second adjustable delay element assembly coupled in series between an output of the second logic gate and an input of the first logic gate; and a digitizing circuit coupled to an output of the second adjustable delay element, wherein the digitizing circuit comprises; an asynchronous counter, wherein an input of the asynchronous counter is coupled to the output of the second adjustable delay element; and a sampling circuit to sample an output of the asynchronous counter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of generating a random number, comprising:
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passing a first signal from a first logic gate into a first adjustable delay element assembly; passing a second signal from the first adjustable delay element assembly into a second logic gate; passing a third signal from the second logic gate into a second adjustable delay element assembly; passing a fourth signal from the second adjustable delay element assembly into the first logic gate; passing the fourth signal into a digitizing circuit; and producing the random number with the digitizing circuit, wherein producing the random number with the digitizing circuit comprises; passing the fourth signal into an asynchronous counter; and sampling an output of the asynchronous counter. - View Dependent Claims (12, 13, 14, 15)
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16. A system, comprising:
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two logic gates; two adjustable delay element assemblies, each of the two adjustable delay element assemblies being coupled between the two logic gates, each of the two adjustable delay element assemblies having a first sub-assembly arranged to provide a fixed delay and a second sub-assembly arranged to provide a selectable delay; a digitizing circuit coupled to an output of one of the two adjustable delay element assemblies, the digitizing circuit having; an asynchronous counter coupled to one of the two adjustable delay element assemblies; and a sampling circuit to sample an output of the asynchronous counter. - View Dependent Claims (17, 18, 19, 20)
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Specification