Execution order block for graphical programming

• US 10,445,072 B1
• Filed: 01/10/2017
• Issued: 10/15/2019
• Est. Priority Date: 01/11/2016
• Status: Active Grant

• Current Assignee: Altair Engineering Incorporated
• Original Assignee: Altair Engineering Incorporated
• Inventors: Darnell, Peter
• Primary Examiner(s): Coyer, Ryan D.
• Application Number:
  US15/402,543
• Time in Patent Office: 1,008 Days
• Field of Search: 717105
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 8/35 model driven
• CPC Class Codes: G06F 8/36 Software reuse
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

A graphical block diagram can use an execution order block to enforce an execution order for parallel subtrees. A graphical data flow block diagram is generated that includes parallel subtrees. The parallel subtrees can be connected to input pins of the execution order block in the execution order. The parallel subtrees are processed in the execution order before other blocks connected to the parallel subtrees are processed according to the normal execution order of the graphical program. The execution order of the execution order block is not affected by the other blocks, and the normal execution order of the other blocks according to the graphical program is not affected by the execution order of the execution order block. The techniques described herein improve a model-based development platform.

Claims

1. An apparatus for specifying an execution order of subtrees in a graphical block diagram, comprising:

one or more processors; and

one or more non-transitory computer-readable media including one or more sequences of instructions which, when executed by the one or more processors, causes the one or more processors to perform operations comprising;

receiving data indicating a set of graphical blocks, the set of graphical blocks comprising;

an execution order block including a plurality of input pins, and

a plurality of additional graphical blocks,

wherein each input pin of the plurality of input pins is attached to respective graphical block of the plurality of additional graphical blocks, and

wherein the execution order block defines an execution order of the graphical blocks attached to the plurality of input pins; and

responsive to user input, generating, using a graphical processor, the graphical block diagram for display on an output screen, the graphical block diagram comprising at least some of the graphical blocks of the set of graphical blocks arranged in parallel subtrees of a root graphical block, the root graphical block being selected from among the set of graphical blocks, the parallel subtrees including at least a first subtree and a second subtree, and the graphical block diagram including the execution order block, the plurality of input pins comprising at least a first input pin and a second input pin, the first subtree connected to the first input pin and the second subtree connected to the second input pin; and

interpreting, using a graphical block diagram parser, the graphical block diagram such that, when the graphical block diagram is executed, the first subtree and the second subtree are executed according to the execution order defined by the execution order block.

2. The apparatus of claim 1, wherein the first subtree is connected to the root graphical block by a first graphical block selected from among the set of graphical blocks, the second subtree is connected to the root graphical block by a second graphical block selected from among the set of graphical blocks, and

wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram by interpreting the first graphical block and the second graphical block according to an arrangement of the first graphical block and the second graphical block within a layout of the graphical block diagram such that, regardless of the execution order, the first graphical block and the second graphical block are executed after the first subtree and the second subtree are executed.

3. The apparatus of claim 1, wherein the first subtree is connected to the root graphical block by a first graphical block selected from among the set of graphical blocks, the second subtree is connected to the root graphical block by a second graphical block selected from among the set of graphical blocks, and the execution order is unaffected by the first graphical block and the second graphical block.

4. The apparatus of claim 3, wherein the first graphical block and the first subtree provide an input to a first subtree root graphical block selected from among the set of graphical blocks, the second graphical block and the second subtree provide an input to a second subtree root graphical block selected from among the set of graphical blocks, the first subtree root graphical block is below the second subtree root graphical block in the graphical block diagram as arranged for display on the output screen, and

wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram, at least in part, according to a top-down order as arranged for display on the output screen such that, when the graphical block diagram is executed, the second graphical block is executed before the first graphical block after executing the first subtree and then the second subtree.

5. The apparatus of claim 1, wherein the operations comprise interpreting, using the graphical block diagram parser, the execution order block by sorting the input subtrees to the plurality of input pins of the execution order block in a top-down order as arranged for display on the output screen, the first input pin located above the second input pin.

6. The apparatus of claim 1, wherein the first subtree comprises a first graphical block selected from among the set of graphical blocks that reads a hardware register, the second subtree comprises a second graphical block selected from among the set of graphical blocks that reads the hardware register, and

wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram such that, when executed, the first graphical block reads a first byte of the hardware register before the second graphical block reads a second byte of the hardware register subsequent to the first byte.

7. The apparatus of claim 1, wherein the execution order block is a first execution order block of a plurality of execution order blocks in the graphical block diagram, and

wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram by sorting the plurality of execution order blocks before other graphical blocks of the graphical block diagram.

8. The apparatus of claim 1, wherein the operations comprise interpreting, using the graphical block diagram parser, other graphical blocks connected to the first subtree and the second subtree, at least in part, according to a top-down order as arranged for display on the output screen.

9. The apparatus of claim 1, wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram according to a simulation mode that executes the first subtree and the second subtree according to the execution order before executing other graphical blocks connected to the first subtree and other graphical blocks connected to the second subtree to simulate a response of a processor-controlled system to a layout of the graphical block diagram.

10. The apparatus of claim 1, wherein the operations comprise interpreting, using the graphical block diagram parser, the graphical block diagram according to a code generation mode that generates code to execute the graphical block diagram such that the first subtree is executed before the second subtree, and the second subtree is executed before other graphical blocks attached to the first subtree and other graphical blocks attached to the second subtree.

11. The apparatus of claim 10, wherein the code is C.

12. The apparatus of claim 1, wherein the graphics processor is controlled by at least one processor of the one or more processors,

wherein the graphical block diagram parser is implemented by at least one processor of the one or more processors, and

wherein at least one processor of the one or more processors is configured to compile the graphical block diagram to run on an embedded computer.

13. A method for processing a graphical block diagram, comprising:

receiving, at a computing device, the graphical block diagram comprising a set of graphical blocks, at least some of the graphical blocks of the set of graphical blocks arranged in parallel subtrees of a root graphical block of the set of graphical block, the parallel subtrees including at least a first subtree and a second subtree, and the graphical block diagram including an execution order block of the set of graphical blocks having at least a first input and a second input, the first subtree connected to the first input and the second subtree connected to the second input;

interpreting the graphical block diagram such that, when the graphical block diagram is executed, the first subtree and the second subtree are executed according to an execution order of the execution order block before other graphical blocks of the set of graphical blocks connected to the root graphical block without affecting an execution order of the other graphical blocks, the execution order of the execution order block defined by an ordering of inputs of the execution order block, and the execution order of the other graphical blocks based on a layout of the graphical block diagram.

14. The method of claim 13, wherein the set of graphical blocks comprises at least some graphical blocks defining respective functions, and the graphical block diagram comprises a data flow diagram.

15. The method of claim 13, wherein interpreting the graphical block diagram comprises at least one of:

generating code to implement the graphical block diagram in a standard batch code;

or

executing the graphical block diagram.

16. The method of claim 13, wherein the parallel subtrees include at least a third subtree and a fourth subtree, the third subtree is connected to a third input of the execution order block, and the fourth subtree is connected to a fourth input of the execution order block, and wherein interpreting the graphical block diagram comprises interpreting the graphical block diagram such that, when the graphical block diagram is executed, the first subtree, the second subtree, the third subtree, and the fourth subtree are executed according to the execution order of the execution order block before other graphical blocks of the set of graphical blocks connected to the root graphical block without affecting the execution order of the other graphical blocks.

17. The method of claim 16, wherein the first subtree, the second subtree, the third subtree, and the fourth subtree are arranged relative to the root graphical block such that, without the execution order block, an order in which the first subtree, the second subtree, the third subtree, and the fourth subtree would be executed is different from the execution order of the execution order block.

18. A method for producing a graphical block diagram, comprising:

presenting, for viewing by a user, a set of graphical blocks comprising;

an execution order block having a variable number plurality of inputs and no output,

a plurality of additional graphical blocks,

wherein each input of the plurality of inputs is attached to respective graphical block of the plurality of additional graphical blocks, and

wherein the execution order block defines an execution order of the graphical blocks attached to the plurality of inputs;

generating, responsive to input from the user, the graphical block diagram for display on an output screen, the graphical block diagram comprising at least some of the graphical blocks of the set of graphical blocks arranged in parallel subtrees of a root graphical block, the root graphical block being selected from among the set of graphical blocks, the parallel subtrees including at least a first subtree and a second subtree, and the graphical block diagram including the execution order block, the plurality of inputs comprising at least a first input and a second input, the first subtree connected to the first input and the second subtree connected to the second input; and

interpreting the graphical block diagram such that, when the graphical block diagram is executed, the first subtree and the second subtree are executed according to the execution order defined by the execution order block.

19. The method of claim 18, wherein the first subtree is connected to a first subtree root block of the root graphical block, the second subtree is connected to a second subtree root block of the root graphical block, the first substrate root block and the second subtree root block being selected from among the set of graphical blocks, the second subtree root block being above the first subtree root block in a layout of the graphical block diagram as displayed on the output screen, and

wherein interpreting the graphical block diagram comprises executing the first subtree, executing the second subtree after executing the first subtree, executing the second subtree root block after executing the second subtree, and executing the first subtree root block after executing the second subtree root block.