Core prioritization for heterogeneous on-chip networks

• US 10,445,131 B2
• Filed: 04/24/2014
• Issued: 10/15/2019
• Est. Priority Date: 04/24/2014
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Solihin, Yan
• Primary Examiner(s): Zhao, Bing
• Application Number:
  US15/306,004
• Publication Number:
  US 20170046198A1
• Time in Patent Office: 2,000 Days
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/4818 Priority circuits therefor
• CPC Class Codes: G06F 9/505 considering the load
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A processor may comprise a plurality of cores operating at heterogeneous frequencies communicatively coupled by a network of routers also operating at heterogeneous frequencies. A core may be prioritized for thread execution based on operating frequencies of routers on a path from the core to a memory controller. Relatively higher priority may be assigned to cores having a path comprising only routers operating at a relatively higher frequency. A combined priority for thread execution may be based on core frequency, router frequency, and the frequency of routers on a path from the core to a memory controller. A core may be selected based primarily on core operating frequency when cache misses fall below a threshold value.

Claims

1. A system, comprising:

a processor comprising a plurality of cores, a plurality of routers, and one or more memory controllers communicatively coupled to the plurality of cores by the plurality of routers, wherein the one or more memory controllers and the plurality of routers are coupled in a network configuration for communication between the one or more memory controllers and the plurality of cores, and wherein the plurality of routers are interconnected to form a plurality of paths from the plurality of cores to the one or more memory controllers; and

a component configured at least to perform or control performance of operations that comprise;

assign a first priority to a first core of the plurality of cores, wherein assignment of the first priority to the first core is based at least, in part, on a first determination that all routers in at least one path between the first core and at least one memory controller, of the one or more memory controllers, are operable at a first frequency;

assign a second priority to a second core of the plurality of cores, wherein assignment of the second priority to the second core is based at least, in part, on a second determination that all paths between the second core and a memory controller, of the one or more memory controllers, comprise at least one router with a maximum operable frequency less than the first frequency, and wherein the second priority is lower than the first priority;

assign a first thread to execute on the first core based on the assigned first priority and second priority to the first core and the second core respectively;

assign a second thread to execute on the second core based at least, in part, on a determination that the first core is unavailable to execute the second thread; and

cause an unassigned core of the plurality of cores to enter a sleep state, based at least, in part, on the second determination.

2. The system of claim 1, wherein the operations further comprise:

cause a router of the plurality of routers to enter a sleep state based at least, in part, on an additional determination that a maximum operable frequency of the router to be caused to enter the sleep state is less than the first frequency.

3. The system of claim 1, wherein the operations further comprise:

determine to assign an additional thread to execute on a core other than the first core, based at least, in part, on a maximum operable frequency of the first core.

4. The system of claim 1, wherein the operations further comprise:

determine to assign an additional thread to a core other than the first core, based at least, in part, on a cache miss rate of the additional thread being above a threshold value.

5. The system of claim 1, wherein the operations further comprise:

calculate a priority value for the first core based at least, in part, on an operable frequency of the first core, an operable frequency of a router nearest to the first core, and a minimum operable frequency of the routers on the at least one path to the at least one memory controller, wherein the priority value corresponds to the first priority.

6. The system of claim 5, wherein the operations further comprise:

assign a first additional thread to execute on the first core, wherein assignment of the first additional thread is based at least, in part, on the priority value and an additional determination that a cache miss rate of the first additional thread is above a threshold; and

assign a second additional thread to execute on the second core, wherein assignment of the second additional thread is based at least, in part, on the additional determination that the cache miss rate of the first additional thread is below the threshold.

7. The system of claim 1, wherein the component includes an operating system or a hypervisor.

8. The system of claim 1, wherein the operations further comprise:

determine a priority of a memory controller, of the one or more memory controllers, based at least, in part, on the first determination; and

steer data, based on the priority of the memory controller, to a memory accessible to the memory controller.

9. A non-transitory computer readable storage medium that includes executable instructions stored thereon that, in response to execution by a computation device, cause the computation device to perform or control performance of operations that comprise:

assign a first priority to a first core of a plurality of cores of a processor, wherein assignment of the first priority to the first core is based at least, in part, on a first determination that all routers in at least one path between the first core and at least one memory controller, of one or more memory controllers of the processor, are operable at a first frequency, wherein the processor comprises a plurality of routers that are arranged in a network configuration for communication between the one or more memory controllers and the plurality of cores, and that are interconnected to form a plurality of paths from the plurality of cores to the one or more memory controllers;

assign a second priority to a second core of the plurality of cores, wherein assignment of the second priority to the second core is based at least, in part, on a second determination that all paths between the second core and a memory controller, of the one or more memory controllers, comprise at least one router with a maximum operable frequency less than the first frequency, and wherein the second priority is lower than the first priority;

assign a first thread to execute on the first core based on the assigned first priority and second priority to the first core and the second core respectively;

assign a second thread to execute on the second core based at least, in part, on a determination that the first core is unavailable to execute the second thread; and

cause an unassigned core of the plurality of cores to enter a sleep state, based at least, in part, on the second determination.

10. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

determine to assign an additional thread to execute on a core other than the first core, based at least, in part, on a maximum operable frequency of the first core.

11. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

evaluate information indicative of operable frequencies of routers on a path from the first core to the at least one memory controller.

12. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

calculate a priority value for the first core based at least, in part, on an operable frequency of the first core, an operable frequency of a router nearest to the first core, and a minimum operable frequency of the routers on the at least one path to the at least one memory controller, wherein the priority value corresponds to the first priority.

13. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

assign an additional thread to execute on the first core, wherein the assignment of the additional thread is based at least, in part, on the first priority and an additional determination that a cache miss rate of the additional thread is above a threshold.

14. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

assign an additional thread to execute on the second core in response to a determination that a cache miss rate of the additional thread is below a threshold and in response to determination that a maximum operable frequency of the second core is greater than a maximum operable frequency of the first core.

15. The non-transitory computer readable storage medium of claim 9, further comprising instructions stored thereon that, in response to execution by the computation device, cause the computation device to perform or control performance of at least one operation that comprises:

associate a memory for the first thread with a physical page frame served by a particular memory controller, wherein the particular memory controller is selected based at least, in part, on the first determination.