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Memory device that communicates error correction results to a host

  • US 10,445,174 B2
  • Filed: 02/22/2017
  • Issued: 10/15/2019
  • Est. Priority Date: 08/28/2015
  • Status: Active Grant
First Claim
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1. A memory device, comprising:

  • a semiconductor memory cell array;

    a controller circuit configured to communicate with an external device through an interface conforming to Serial Peripheral Interface (SPI) and read data stored in a page of the semiconductor memory cell array in response to a read command received through the interface;

    an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each of a plurality of units that forms the page;

    a first pin through which a chip select signal is received;

    a second pin through which a clock signal is received; and

    a third pin through which a command and data are received in synchronization with the clock signal, whereinthe controller circuit is further configured to transmit, through the interface to the external device, information about a number of error bits detected by the ECC circuit in data read from at least one of the units of the page, andthe controller circuit recognizes a first portion of a signal received by the third pin after the chip select signal is asserted as a command.

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