Memory device that communicates error correction results to a host

• US 10,445,174 B2
• Filed: 02/22/2017
• Issued: 10/15/2019
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kodera, Shunsuke, Kitazume, Toshihiko, Kada, Kenichirou, Tsuji, Nobuhiro, Takeda, Shinya, Iwata, Tetsuya, Furuyama, Yoshio, Narai, Hirosuke
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US15/439,886
• Publication Number:
  US 20170160946A1
• Time in Patent Office: 965 Days
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/0605 by facilitating the interaction with a user or administrator
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.

Claims

1. A memory device, comprising:

a semiconductor memory cell array;

a controller circuit configured to communicate with an external device through an interface conforming to Serial Peripheral Interface (SPI) and read data stored in a page of the semiconductor memory cell array in response to a read command received through the interface;

an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each of a plurality of units that forms the page;

a first pin through which a chip select signal is received;

a second pin through which a clock signal is received; and

a third pin through which a command and data are received in synchronization with the clock signal, wherein

the controller circuit is further configured to transmit, through the interface to the external device, information about a number of error bits detected by the ECC circuit in data read from at least one of the units of the page, and

the controller circuit recognizes a first portion of a signal received by the third pin after the chip select signal is asserted as a command.

2. The memory device according to claim 1, wherein

the information is the number of error bits detected by the ECC circuit in data read from said at least one of the units of the page.

3. The memory device according to claim 1, wherein

the information indicates the number of error bits detected and corrected by the ECC circuit in data read from said at least one of the units of the page.

4. The memory device according to claim 1, wherein

the information indicates that the number of error bits detected is greater than a certain value and the error bits were not corrected.

5. The memory device according to claim 4, wherein

the controller circuit includes a storage region in which operational settings of the memory device are stored, the operational settings including a first entry for storing the certain value and a second entry for storing the information.

6. The memory device according to claim 5, wherein

the certain value in the first entry is settable through a command received from the external device through the interface.

7. The memory device according to claim 5, wherein

the controller circuit transmits the information to the external device, in response to a command to read the second entry, which is received through the interface.

8. The memory device according to claim 1, wherein each of the units corresponds to a sector.

9. A memory device, comprising:

a first pin through which a chip select signal is received from an external device;

a second pin through which a signal is output to the external device;

a third pin through which a signal is received from the external device;

a fourth pin through which a clock is received from the external device;

a semiconductor memory cell array;

a controller circuit configured to recognize that a first portion of the signal received by the third pin in synchronization with the clock after assertion of the chip select signal is a command, and read data stored in a page of the semiconductor memory cell array in response to a read command received through the third pin; and

an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each of a plurality of units that forms the page, wherein

the controller circuit is further configured to transmit, through the second pin to the external device, information about a number of error bits detected by the ECC circuit in the data read from at least one of the units of the page.

10. The memory device according to claim 9, wherein

the information indicates the number of error bits detected by the ECC circuit in data read from said at least one of the units of the page.

11. The memory device according to claim 9, wherein

the information indicates the number of error bits detected and corrected by the ECC circuit in data read from said at least one of the units of the page.

12. The memory device according to claim 9, wherein

the information indicates that the number of error bits detected is greater than a certain value and the error bits were not corrected.

13. The memory device according to claim 12, wherein

the controller circuit includes a storage region in which operational settings of the memory device are stored, the operational settings including a first entry for storing the certain value and a second entry for storing the information.

14. The memory device according to claim 13, wherein

the certain value in the first entry is settable through a command received from the external device through the third pin.

15. The memory device according to claim 13, wherein

the controller circuit transmits the information to the external device through the second pin, in response to a command to read the second entry, which is received through the third pin.

16. The memory device according to claim 9, wherein each of the units corresponds to a sector.

17. The memory device according to claim 9, wherein

the controller circuit is configured to communicate with the external device through an interface conforming to Serial Peripheral Interface (SPI).