Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
First Claim
1. A memory controller integrated circuit to control flash memory, the flash memory comprising flash memory dies, the flash memory dies each comprising structures at a common hierarchical level, the memory controller integrated circuit comprising:
- a host interface to receive read requests and associated addresses from a host;
a memory interface to send memory commands to the flash memory dies in response to the read requests received from the host;
logic to control satisfaction of the memory commands in the flash memory dies in response to the read requests received from the host;
wherein the logic comprises at least one of (1) hardware circuit elements or (2) instructions stored on non-transitory storage which, when executed, are to control circuitry of said memory controller integrated circuit;
wherein the logic, for at least a given one of the read requests, is to interpret the given one as directed to data stored across two or more of the flash memory dies, said logic to process the address associated with the given one to identify a common address offset to be independently applied to each of the two or more of the flash memory dies; and
wherein the logic is to direct the memory commands such that each of the two or more of the flash memory dies is provided with a physical address, dependent on identification of the common address offset, with which to retrieve the data stored across the two or more of the flash memory dies.
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Accused Products
Abstract
This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.
221 Citations
20 Claims
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1. A memory controller integrated circuit to control flash memory, the flash memory comprising flash memory dies, the flash memory dies each comprising structures at a common hierarchical level, the memory controller integrated circuit comprising:
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a host interface to receive read requests and associated addresses from a host; a memory interface to send memory commands to the flash memory dies in response to the read requests received from the host; logic to control satisfaction of the memory commands in the flash memory dies in response to the read requests received from the host; wherein the logic comprises at least one of (1) hardware circuit elements or (2) instructions stored on non-transitory storage which, when executed, are to control circuitry of said memory controller integrated circuit; wherein the logic, for at least a given one of the read requests, is to interpret the given one as directed to data stored across two or more of the flash memory dies, said logic to process the address associated with the given one to identify a common address offset to be independently applied to each of the two or more of the flash memory dies; and wherein the logic is to direct the memory commands such that each of the two or more of the flash memory dies is provided with a physical address, dependent on identification of the common address offset, with which to retrieve the data stored across the two or more of the flash memory dies. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A storage drive, comprising:
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flash memory comprising flash memory dies, the flash memory dies each comprising structures at a common hierarchical level; and a memory controller integrated circuit to control the flash memory, the memory controller integrated circuit comprising a host interface to receive read requests and associated addresses from a host, a memory interface to send memory commands to the flash memory dies in response to the read requests received from the host, and logic to control satisfaction of the memory commands in the flash memory dies in response to the read requests received from the host; wherein the logic comprises at least one of (1) hardware circuit elements or (2) instructions stored on non-transitory storage which, when executed, are to control circuitry of said memory controller integrated circuit; wherein the logic, for at least a given one of the read requests, is to interpret the given one as directed to data stored across two or more of the flash memory dies, said logic to process the address associated with the given one to identify a common address offset to be independently applied to each of the two or more of the flash memory dies; and wherein the logic is to direct the memory commands such that each of the two or more of the flash memory dies is provided with a physical address, dependent on identification of the common address offset, with which to retrieve the data stored across the two or more of the flash memory dies. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification