Managing block arrangement of super blocks

• US 10,445,230 B2
• Filed: 12/08/2017
• Issued: 10/15/2019
• Est. Priority Date: 12/08/2017
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Liu, Ting-Yu
• Primary Examiner(s): Chery, Mardochee
• Application Number:
  US15/836,476
• Publication Number:
  US 20190179741A1
• Time in Patent Office: 676 Days
• Field of Search: 711170
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes.

Claims

1. A memory controller for managing block arrangement of super blocks in a memory, the memory controller comprising:

control circuitry coupled to the memory having at least two planes of physical blocks and configured to

maintain block information of each individual physical block in the planes, wherein the block information of the physical block comprises at least one of erase count, valid count, read counts of pages, erase delay time, a first flag indicating whether the physical block is in a current data block, or a second flag indicating whether the physical block is an unused block;

combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes; and

in response to a determination that a number of unused blocks in a plane is no smaller than a reclaim threshold and that there is an urgent block in the plane, pick the urgent block as a victim block.

2. The memory controller of claim 1, wherein the control circuitry is configured to, for each of the planes, select an unused physical block having a minimum erase count in the physical blocks of the plane based on the block information of the physical blocks of the plane.

3. The memory controller of claim 2, wherein the control circuitry is configured to:

determine a threshold based on the erase counts of the selected unused physical blocks from the planes;

in response to a determination that a selected unused physical block has an erase count larger than the determined threshold, determine not to select the selected unused physical block for the super block; and

in response to a determination that a selected unused physical block has an erase count no larger than the determined threshold, select the selected unused physical block for the super block.

4. The memory controller of claim 1, wherein the control circuitry is configured to:

determine a respective sum of valid counts of physical blocks in each of the planes;

compare the respective sums of valid counts of the planes; and

determine, based on a result of the comparison, whether to select a physical block from one of the planes for the super block.

5. The memory controller of claim 1, wherein the control circuitry is configured to:

determine a respective maximum value of erase count of physical blocks in each of the planes;

select a plane having the respective maximum value of erase counts that is smaller than a maximum of the respective maximum values of erase counts;

select unused physical blocks in the selected plane, wherein an erase delay time of each of the selected unused physical blocks is larger than a minimum of erase delay times of physical blocks in the selected plane; and

select a physical block with a minimum erase count among the selected unused physical blocks.

6. The memory controller of claim 1, wherein the control circuitry is configured to:

in response to a determination that the super block is incapable of storing more data, release the super block to obtain individual data blocks.

7. The memory controller of claim 1, wherein the control circuitry is configured to:

in response to a determination that a second number of unused blocks in a second plane is smaller than a second reclaim threshold, pick a second physical block with a minimum valid count in the second plane as a second victim block.

8. The memory controller of claim 1, wherein the control circuitry is configured to determine a physical block to be an urgent block by determining at least one of:

that a program failure has occurred in the physical block,

that a number of error bits in the physical block exceeds a first threshold, or

that the number of error bits in the physical block is smaller than the first threshold and exceeds a second threshold, the second threshold being smaller than the first threshold.

11. The memory controller of claim 1, wherein the control circuitry is configured to:

arrange valid data in one or more victim blocks from one or more planes to be migrated based on one or more reclaim priority polices; and

migrate the valid data simultaneously to a current data block.

12. The memory controller of claim 1, wherein the control circuitry is configured to:

erase a victim block having no valid data to obtain an unused physical block.

13. The memory controller of claim 1, wherein the control circuitry is configured to determine one or more characteristics of data to be written in the memory,

wherein the data includes at least one of data from a device external from the memory, valid data to be migrated from the memory, or metadata associated with the memory, and

wherein the characteristics include at least one of a security level, an internal system level, or a level of read &

write frequency.

14. The memory controller of claim 13, wherein the control circuitry is configured to:

combine the physical blocks from each of the planes to the super block based on the determined characteristics of the data to be written.

15. The memory controller of claim 13, wherein the control circuitry is configured to:

in response to a determination that there is no blank super page to store the data, combine the physical blocks from each of the planes to the super block;

erase each of the selected physical blocks based on the determined characteristics of the data to be written; and

combine single pages from the physical blocks in the planes to obtain a super page for storing the data.

16. The memory controller of claim 13, wherein the control circuitry is configured to:

categorize the data based on the determined characteristics of the data;

arrange the data to individual physical blocks in the super block based on the determined characteristics of the data and the block information of the individual physical blocks in the super block; and

program one or more super pages of the super block to store the data.

18. The memory controller of claim 1, wherein the control circuitry is configured to:

pick a plurality of physical blocks from a plurality of respective planes based on the block information of the physical blocks in the planes, at least two of the picked physical blocks having different position numbers in the corresponding respective planes, and

combine the plurality of picked physical blocks from the plurality of respective planes to obtain the super block.

9. A memory controller for managing block arrangement of super blocks in a memory, the memory controller comprising:

control circuitry coupled to the memory having at least two planes of physical blocks and configured to;

maintain block information of each individual physical block in the planes, wherein the block information of the physical block comprises at least one of erase count, valid count, read counts of pages, erase delay time, a first flag indicating whether the physical block is in a current data block, or a second flag indicating whether the physical block is an unused block;

combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes; and

in response to a determination that a number of unused blocks in a plane is no smaller than a reclaim threshold, pick a physical block in the plane as a victim block by comparing a weight value to a predetermined threshold, wherein the weight value of the physical block is determined based on one or more parameters including block type, valid count, erase order, and erase delay time.

10. The memory controller of claim 9, wherein the control circuitry is configured to:

determine a respective number of victim blocks of each of the planes;

select a plane having a maximum of the respective numbers of victim blocks among the planes, the selected plane including one or more other physical blocks having the weight values smaller than the predetermined threshold, wherein a smaller valid count corresponds to a smaller weight value than a larger valid count, and a longer erase delay time corresponds to a smaller weight value than a shorter erase delay time; and

pick the physical block by determining that the physical block is in a logical to physical (L2P) table same as a particular number of victim blocks in the plane and the particular number is higher than that of each of the one or more other physical blocks in the plane.

17. A method of managing block arrangement of super blocks in a memory by a memory controller, the method comprising:

maintaining, by a control circuitry in the memory controller, block information of each individual physical block in at least two planes of the memory;

determining, by the control circuitry, one or more characteristics of data to be written in the memory;

combining, by the control circuitry, one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes and the determined characteristics of the data; and

in response to a determination that a number of unused blocks in a plane is no smaller than a reclaim threshold and that there is an urgent block in the plane, picking the urgent block as a victim block.