Method, system, and apparatus for page sizing extension
First Claim
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1. A processor, comprising:
- a plurality of cores, one or more of the plurality of cores including execution resources to execute instructions;
an instruction address translation circuit coupled to the one or more of the plurality of cores to perform address translations for instructions, the instruction address translation circuit to translate virtual addresses to physical addresses of memory pages containing the instructions;
a data address translation circuit coupled to the one or more of the plurality of cores to perform address translations for data, the data address translation circuit to translate virtual addresses to physical addresses of memory pages containing the data; and
one or both of the instruction address translation circuit and the data address translation circuit storing a plurality of entries, one or more of the entries to contain at least one virtual to physical address translation, the plurality of entries including a first plurality of entries and a second plurality of entries, the second plurality of entries corresponding to memory pages having different sizes than memory pages corresponding to the first plurality of entries,one or more of the cores to set one or more bits in the plurality of entries to identify a page size associated with a memory page, the one or more bits to distinguish between 4 Kbyte pages, 64 Kbyte pages, and 4 Mbyte pages, wherein a plurality of sequential 4 Kbyte pages having corresponding consecutive entries from the plurality of entries are to be combined into and treated as the 64 Kbyte pages or the 4 Mbyte pages;
wherein an entry is to further include;
a cacheable indication to identify whether a memory page associated with the entry is cacheable; and
one or more supervisor/user indications to identify types of execution modes in which the memory page may be read and written.
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Abstract
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
13 Citations
18 Claims
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1. A processor, comprising:
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a plurality of cores, one or more of the plurality of cores including execution resources to execute instructions; an instruction address translation circuit coupled to the one or more of the plurality of cores to perform address translations for instructions, the instruction address translation circuit to translate virtual addresses to physical addresses of memory pages containing the instructions; a data address translation circuit coupled to the one or more of the plurality of cores to perform address translations for data, the data address translation circuit to translate virtual addresses to physical addresses of memory pages containing the data; and one or both of the instruction address translation circuit and the data address translation circuit storing a plurality of entries, one or more of the entries to contain at least one virtual to physical address translation, the plurality of entries including a first plurality of entries and a second plurality of entries, the second plurality of entries corresponding to memory pages having different sizes than memory pages corresponding to the first plurality of entries, one or more of the cores to set one or more bits in the plurality of entries to identify a page size associated with a memory page, the one or more bits to distinguish between 4 Kbyte pages, 64 Kbyte pages, and 4 Mbyte pages, wherein a plurality of sequential 4 Kbyte pages having corresponding consecutive entries from the plurality of entries are to be combined into and treated as the 64 Kbyte pages or the 4 Mbyte pages; wherein an entry is to further include; a cacheable indication to identify whether a memory page associated with the entry is cacheable; and one or more supervisor/user indications to identify types of execution modes in which the memory page may be read and written. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method comprising:
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executing instructions on execution resources of one or more cores; performing address translations for instructions using an instruction address translation circuit coupled to the one or more of the plurality of cores, wherein performing address translations includes translating virtual addresses to physical addresses of memory pages containing the instructions; performing address translations for data using a data address translation circuit coupled to the one or more of the plurality of cores, wherein performing address translations includes translating virtual addresses to physical addresses of memory pages containing the data; wherein performing the address translations further includes performing a lookup on a plurality of entries, one or more of the entries to contain at least one virtual to physical address translation, the plurality of entries including a first plurality of entries and a second plurality of entries, the second plurality of entries corresponding to memory pages having different sizes than memory pages corresponding to the first plurality of entries; and setting one or more bits in the plurality of entries to identify a page size associated with a memory page, the one or more bits to distinguish between 4 Kbyte pages, 64 Kbyte pages, and 4 Mbyte pages, wherein a plurality of sequential 4 Kbyte pages having corresponding consecutive entries from the plurality of entries are to be combined into and treated as the 64 Kbyte pages or the 4 Mbyte pages; wherein an entry is to further include; a cacheable indication to identify whether a memory page associated with the entry is cacheable; and one or more supervisor/user indications to identify types of execution modes in which the memory page may be read and written. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A processor comprising:
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means for executing instructions on execution resources of one or more cores; instruction address translation means for performing address translations for instructions, wherein performing address translations includes translating virtual addresses to physical addresses of memory pages containing the instructions; data address translation means for performing address translations for data, wherein performing address translations includes translating virtual addresses to physical addresses of memory pages containing the data; wherein performing the address translations further includes performing a lookup on a plurality of entries, one or more of the entries to contain at least one virtual to physical address translation, the plurality of entries including a first plurality of entries and a second plurality of entries, the second plurality of entries corresponding to memory pages having different sizes than memory pages corresponding to the first plurality of entries; and means for setting one or more bits in the plurality of entries to identify a page size associated with a memory page, the one or more bits to distinguish between 4 Kbyte pages, 64 Kbyte pages, and 4 Mbyte pages, wherein a plurality of sequential 4 Kbyte pages having corresponding consecutive entries from the plurality of entries are to be combined into and treated as the 64 Kbyte pages or the 4 Mbyte pages; wherein an entry is to further include; a cacheable indication to identify whether a memory page associated with the entry is cacheable; and one or more supervisor/user indications to identify types of execution modes in which the memory page may be read and written. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification