Bit reordering for memory devices

• US 10,445,259 B2
• Filed: 04/18/2017
• Issued: 10/15/2019
• Est. Priority Date: 04/18/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Lucky, Richard S., Ellis, Robert W.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Daley, Christopher
• Application Number:
  US15/490,724
• Publication Number:
  US 20180300266A1
• Time in Patent Office: 910 Days
• CPC Class Codes: G06F 13/1626 by reordering requests
• CPC Class Codes: G06F 13/4063 Device-to-bus coupling

Abstract

The present disclosure discloses a memory device including a controller for bit reordering. The controller receives an input bit sequence including a plurality of bits with a first bit order. The controller identifies a physical location of a non-volatile memory element in the memory device and determines a correspondence between the first bit order and a second bit order based on the physical location. The controller generates an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

Claims

1. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations; and

a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller;

wherein the controller is configured to;

receive an input bit sequence including a plurality of bits with a first bit order from a first non-volatile memory element of the plurality of non-volatile memory elements, wherein the controller writes the input bit sequence to a first memory device stored in the controller;

identify a physical location of the first non-volatile memory element in the first memory device stored in the controller;

determine a correspondence between the first bit order and a second bit order based on the physical location; and

generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

2. The memory device of claim 1, wherein the correspondence between the first bit order and the second bit order indicates a bit-to-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

3. The memory device of claim 1, wherein the controller is further configured to store the correspondence between the first bit order and the second bit order in a look-up table stored in the first memory device stored in the controller.

4. The memory device of claim 1, wherein the input bit sequence is received from the controller and the output bit sequence is transmitted to the non-volatile memory element.

5. A memory device, comprising:

a plurality of processing means configured to process a plurality of read and/or write operations; and

a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means;

wherein the controlling means is configured to;

receive an input bit sequence including a plurality of bits with a first bit order from a first processing means of the plurality of processing means, wherein the controlling means writes the input bit sequence to a first memory device stored in the controlling means;

identify a physical location of the first processing means in the first memory device stored in the controlling means;

determine a correspondence between the first bit order and a second bit order based on the physical location; and

generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

6. The memory device of claim 5, wherein the memory device comprises a Solid State Drive (SSD).

7. The memory device of claim 5, wherein the correspondence between the first bit order and the second bit order indicates a bit-to-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

8. The memory device of claim 5, wherein the controlling means is further configured to store the correspondence between the first bit order and the second bit order in a look-up table stored in the first memory device stored in the controlling means.

9. The memory device of claim 5, wherein the correspondence between the first bit order and the second bit order comprises an arbitrary correspondence.

10. The memory device of claim 5, wherein the input bit sequence is received from the controlling means and the output bit sequence is transmitted to the processing means.

11. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read and/or write operations; and

a controller connected to the plurality of non-volatile memory elements via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of non-volatile memory elements to the controller;

wherein the controller is configured to;

receive an input bit sequence including a plurality of bits with a first bit order from a first non-volatile memory element of the plurality of non-volatile memory elements, wherein the controller reads the input bit sequence from one of the plurality of non-volatile memory elements;

identify a physical location of the first non-volatile memory element in a first memory device stored in the controller;

determine a correspondence between the first bit order and a second bit order based on the physical location;

generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and

transmit the output bit sequence to a processor in the controller for processing.

12. The memory device of claim 11, wherein the input bit sequence is received from the first non-volatile memory element.

13. The memory device of claim 11, wherein the controller comprises one or more selectors to generate the output bit sequence.

14. The memory device of claim 11, wherein each of the one or more buses constructs an 8-bit channel between the controller and the plurality of non-volatile memory elements.

15. A memory device, comprising:

a plurality of processing means configured to process a plurality of read and/or write operations; and

a controlling means connected to the plurality of processing means via one or more buses, wherein each of the one or more buses is configured to connect at least two of the plurality of processing means to the controlling means;

wherein the controlling means is configured to;

receive an input bit sequence including a plurality of bits with a first bit order from a first processing means of the plurality of processing means, wherein the controlling means reads the input bit sequence from one of the plurality of processing means;

identify a physical location of the processing means in a first memory device stored in the controlling means;

determine a correspondence between the first bit order and a second bit order based on the physical location;

generate an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and

transmit the output bit sequence to a processor in the controlling means for processing.

16. The memory device of claim 15, wherein the memory device comprises a Solid State Drive (SSD).

17. The memory device of claim 15, wherein the correspondence between the first bit order and the second bit order indicates a bit-to-bit correspondence between each bit in the input bit sequence and each bit in the output bit sequence.

18. The memory device of claim 15, wherein the controlling means is further configured to store the correspondence between the first bit order and the second bit order in a look-up table stored in the first memory device stored in the controlling means.

19. The memory device of claim 15, wherein the correspondence between the first bit order and the second bit order comprises an arbitrary correspondence.

20. The memory device of claim 15, wherein the input bit sequence is received from the first processing means.

21. A method, comprising:

receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order from a first non-volatile memory element of a plurality of non-volatile memory elements, wherein the controller writes the input bit sequence to a first memory device stored in the controller;

identifying a physical location of the first non-volatile memory element in the first memory device stored in the controller;

determining a correspondence between the first bit order and a second bit order based on the physical location; and

generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence.

22. The method of claim 21, wherein the memory device comprises a Solid State Drive (SSD).

23. The method of claim 21, wherein each of the non-volatile memory elements comprises a NAND die.

24. The method of claim 21, wherein the controller comprises a NAND controller.

25. A method, comprising:

receiving, by a controller in a memory device, an input bit sequence including a plurality of bits with a first bit order from a first non-volatile memory element of a plurality of non-volatile memory elements, wherein the controller reads the input bit sequence from one of the plurality of non-volatile memory elements in the memory device;

identifying a physical location of the first non-volatile memory element in a first memory device stored in the controller;

determining a correspondence between the first bit order and a second bit order based on the physical location;

generating an output bit sequence including the plurality of bits with the second bit order based on the correspondence; and

transmitting the output bit sequence to a processor in the controller for processing.

26. The method of claim 25, wherein the correspondence between the first bit order and the second bit order comprises an arbitrary correspondence.

27. The method of claim 25, wherein the plurality of non-volatile memory elements are packaged in one or more ball grid array (BGA) packages.

28. The method of claim 25, wherein the controller is connected to the plurality of non-volatile memory elements via multiple buses.