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Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction features

  • US 10,445,451 B2
  • Filed: 07/01/2017
  • Issued: 10/15/2019
  • Est. Priority Date: 07/01/2017
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of processing elements, wherein at least one of the processing elements is to perform a floating-point operation with selectable precision control; and

    an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform an operation when an incoming operand set arrives at the plurality of processing elements.

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