Interactive routing with poly vias

• US 10,445,459 B1
• Filed: 08/28/2017
• Issued: 10/15/2019
• Est. Priority Date: 08/28/2017
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Tatara, Eric, Neal, Brett
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US15/688,377
• Time in Patent Office: 778 Days
• Field of Search: 716106
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 3/0005 for designing circuits by computer
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4611 by laminating two or more circuit boards H05K3/4652 takes precedence

Abstract

The present embodiments are directed generally to techniques for providing an interactive environment that gives visual feedback and indicators to identify and/or encourage effective sharing of partially used drill sites, all inside a typical etch-edit environment. Such an interactive environment allows designers to effectively leverage and exploit new PCB manufacturing techniques that allow for multi-net use of a single drill hole.

Claims

1. A method of implementing a layout of a circuit in a circuit structure, comprising:

identifying a trace of the layout, the trace having an associated layer in the circuit structure;

identifying another layer in the circuit structure to which the trace needs to transition;

identifying an existing via in the layout;

determining whether the existing via can be used to connect to the trace for transitioning to the another layer, wherein determining whether the existing via can be used includes determining whether the existing via is comprised of a drill hole that allows use by multiple nets; and

adjusting a graphical indicator associated with the existing via in a display of the layout based on the determination.

2. The method of claim 1, wherein determining whether the existing via can be used includes determining whether one or more other traces are currently connected to the existing via.

3. The method of claim 2, wherein determining whether the existing via can be used further includes, if one or more other traces are currently connected to the existing via, and if the existing via is comprised of a drill hole that allows use by multiple nets, determining whether the another layer is in a portion of the drill hole not connected to by the one or more other traces.

4. The method of claim 2, wherein determining whether the existing via can be used further includes, if one or more other traces are currently connected to the existing via, determining whether the one or more other traces belong to a same net as the trace.

5. The method of claim 1, wherein without the adjusting, the existing via is displayed with one or more circles, and wherein adjusting the graphical indicator includes displaying one or more geometric shapes around the one or more circles based on the determination of whether the existing via can be used.

6. The method of claim 1, further comprising allowing the display of the trace to be snapped to the display of the existing via if it is determined the existing via can be used for connecting.

7. The method of claim 1, wherein the circuit structure comprises a printed circuit board.

8. A method of implementing a layout of a circuit in a circuit structure, comprising:

identifying a trace of the layout, the trace having an associated layer in the circuit structure and a via for transitioning the trace to another layer in the circuit structure;

identifying an existing via in the layout;

determining whether the via of the trace with the existing via for transitioning the trace to the another layer, wherein determining whether the existing via can be merged includes determining whether the existing via is comprised of a drill hole that allows use by multiple nets; and

adjusting a graphical indicator associated with the existing via in a display of the layout based on the determination of whether the vias can be merged.

9. The method of claim 8, wherein determining whether the existing via can be merged includes determining whether one or more other traces are currently connected to the existing via.

10. The method of claim 9, wherein determining whether the existing via can be merged further includes, if one or more other traces are currently connected to the existing via, and if the existing via is comprised of a drill hole that allows use by multiple nets, determining whether the another layer is in a portion of the drill hole not connected to by the one or more other traces.

11. The method of claim 9, wherein determining whether the existing via can be used further includes, if one or more other traces are currently connected to the existing via, determining whether the one or more other traces belong to a same net as the trace.

12. The method of claim 8, wherein without the adjusting, the existing via is displayed with one or more circles, and wherein adjusting the graphical indicator includes displaying one or more geometric shapes around the one or more circles based on the determination of whether the vias can be merged.

13. The method of claim 8, wherein determining whether the existing via can be merged further includes comparing widths of the via and the existing via.

14. The method of claim 13, wherein without the adjusting, the existing via is displayed with one or more circles, and wherein adjusting the graphical indicator includes overlaying one or more geometric shapes over the one or more circles if the widths of the via and the existing via are different.

15. The method of claim 8, further comprising allowing the display of the via to be snapped to the display of the existing via if it is determined the vias can be merged.

16. The method of claim 8, wherein the circuit structure comprises a printed circuit board.

17. A system for implementing a layout of a circuit in a circuit structure, comprising:

a user interface module that is configured to allow a user to identify a trace of the layout, the trace having an associated layer in the circuit structure, the user interface module further being configured to allow the user to identify another layer in the circuit structure to which the trace needs to transition; and

a layout editor coupled to storage containing information about the layout, the layout editor being configured to identify an existing via in the layout based on the information and the identification of the trace from the user interface module, and to determine whether the existing via can be used to connect to the identified trace for transitioning to the another layer,

wherein the layout editor is further configured to interact with the user interface module so as to adjust a graphical indicator associated with the existing via in a display of the layout based on the determination, and

wherein the layout editor is configured to determine whether the existing via can be used by accessing a storage containing information regarding whether the existing via is comprised of a drill hole that allows use by multiple nets, and to determine whether the another layer is in a portion of the drill hole connected to by one or more other traces in the layout.

18. The system of claim 17, wherein without the layout editor performing the adjusting, the existing via is displayed with one or more circles, and wherein adjusting the graphical indicator includes displaying one or more geometric shapes around the one or more circles based on the determination of whether the existing via can be used.

19. The system of claim 17, wherein the circuit structure comprises a printed circuit board.