Image processing apparatus and method

• US 10,445,851 B2
• Filed: 10/17/2016
• Issued: 10/15/2019
• Est. Priority Date: 10/28/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Yong-Bae
• Primary Examiner(s): Tran, Sinh
• Assistant Examiner(s): Gebriel, Selam T
• Application Number:
  US15/295,592
• Publication Number:
  US 20170124678A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management

Abstract

An image processing apparatus is provided. The image processing apparatus includes a memory, a first image processor configured to perform a first image processing operation on image data to generate first data, and a second image processor configured to perform a second image processing operation on the first data to generate second data. In a first operation mode, the first data is directly transferred from the first image processor to the second image processor. When the first operation mode is changed to a second operation mode, the first data is transferred from the first image processor to the second image processor via the memory.

Claims

1. An image processing apparatus comprising:

a memory;

a data input/output (I/O) controller;

a first image processor configured to perform a first Image processing operation on image data to generate first data; and

a second image processor configured to perform a second image processing operation on the first data to generate second data,

wherein the image processing apparatus directly transfers the first data from the first image processor to the second image processor through a signal line directly connecting the first processor and the second processor without accessing the memory, when an operation mode is set to a first operation mode, wherein the first operation mode is a normal mode,

wherein the image processing apparatus indirectly transfers the first data from the first image processor to the second image processor via the memory, when the operation mode is set to a second operation mode, wherein the second operation mode is a zoom mode,

wherein the data (I/O) controller is configured to determine the operation mode, generate a signal indicating the determined operation mode, and output the signal to the first Image processor, and

wherein the first image processor outputs the first data to the second image processor when the outputted signal indicates the first operation mode and outputs the first data to the memory when the outputted signal indicates the second operation mode.

2. The Image processing apparatus of claim 1, wherein the data I/O controller is further configured to determine an input/output (I/O) mode of the first data as one of a first input/output (I/O) mode where the first data is directly transferred from the first image processor to the second image processor and a second input/output (I/O) mode where the first data is transferred from the first image processor to the second image processor via the memory, based on the operation mode.

3. The image processing apparatus of claim 2, wherein the data controller is located outside the first and second image processors.

4. The image processing apparatus of claim 2, wherein the data I/O controller is located within at least one of the first and second image processors.

5. The image processing apparatus of claim 4, wherein the data I/O controller comprises:

a data output controller located within the first image processor, the data output controller for controlling an output of the first data to output the first data to the second image processor in the first I/O mode and output the first data to the memory in the second I/O mode; and

a data input controller located within the second image processor, the data input controller for controlling an input of the first data to receive the first data from the first image processor in the first I/O mode and receive the first data from the memory in the second I/O mode.

6. The image processing apparatus of claim 2, wherein the image data comprises first sub-image data and second sub-image data, wherein the first image processor sequentially performs the first image processing operation on the first sub-image data and the second sub-image data to sequentially generate first sub-data and second sub-data, and wherein the image processing apparatus further comprises a memory controller configured to control the memory to enable the second image processor to read the first sub-data from the memory before the second sub-data is written in the memory after the first sub-data is written in the memory.

7. The image processing apparatus of claim 6, wherein the memory controller is located outside the first and second image processors and supplies a read command for reading the first sub-data from the memory before supplying a write command for writing the first sub-data in the memory.

8. The image processing apparatus of claim 6, wherein the memory controller is located within at least one of the first and second image processors.

9. The image processing apparatus of claim 8, wherein the memory controller comprises:

a first memory controller disposed in the first image processor, the first memory controller configured to record a time when the first sub-data is written in the memory; and

a second memory controller disposed in the second image processor, the second memory controller configured to sense the time when the first sub-data is written to the memory.

10. The image processing apparatus of claim 6, further comprising:

a mode changing controller configured to compare a write pointer and a read pointer received from the memory controller when a zoom end command is applied, and change the I/O mode of the first data from the second I/O mode to the first I/O mode when the write pointer matches the read pointer.

11. The image processing apparatus of claim 10, wherein the mode changing controller is located within the data I/O controller.

12. The image processing apparatus of claim 10, wherein the mode changing controller is located in at least one of the first and second image processors.

13. The image processing apparatus of claim 12, wherein the mode changing controller comprises:

a first mode changing controller located in the first image processor to receive the write pointer; and

a second mode changing controller located in the second image processor to receive the read pointer.

14. The image processing apparatus of claim 6, wherein the second image processor comprises:

an internal buffer; and

a mode changing controller configured to, when a zoom end command is applied, change the I/O mode of the first data from the second I/O mode to the first I/O mode, based on a read pointer received from the memory controller and a buffer pointer of the internal buffer.

15. The image processing apparatus of claim 6, further comprising:

a clock circuit configured to increase a frequency of a clock signal supplied to the second image processor when a zoom end command is applied.

16. An application processor comprising:

a data input/output (I/O) controller;

a first image processor configured to perform a first image processing operation on image data to generate first data; and

a second image processor configured to perform a second image processing operation on the first data to generate second data,

wherein the application processor directly transfers the first data from the first image processor to the second image processor through a signal line directly connecting the first processor and the second processor without accessing a memory when an operation mode is set to a first operation mode, wherein the first operation mode is a normal mode,

wherein the application processor transfers the first data from the first image processor to the second image processor via the memory when the operation mode is set to a second operation mode, wherein the second operation mode is a zoom mode,

wherein the data (I/O) controller is configured to determine the operation mode, generate a signal indicating the determined operation mode, and output the signal to the first Image processor, and

wherein the first image processor outputs the first data to the second image processor when the outputted signal indicates the first operation mode and outputs the first data to the memory when the outputted signal indicates the second operation mode.

17. An image processing apparatus comprising:

a memory controller;

a data input/output (I/O) controller;

a first image processor configured to perform a first image processing operation on image data to generate first data; and

a second image processor configured to perform a second image processing operation on the first data to generate second data,

wherein the image processing apparatus directly transfers the first data from the first image processor to the second image processor through a signal line directly connecting the first processor and the second processor without accessing the memory controller when an operation mode is set to a first operation mode, wherein the first operation mode is a normal mode,

wherein the image processing apparatus transfers the first data from the first image processor to the second image processor via the memory controller when the operation mode is set to a second operation mode, wherein the second operation mode is a zoom mode,

wherein the data (I/O) controller is configured to determine the operation mode, generate a signal indicating the determined operation mode, and output the signal to the first Image processor, and

wherein the first image processor outputs the first data to the second image processor when the outputted signal indicates the first operation mode and outputs the first data to the memory controller when the outputted signal indicates the second operation mode.

18. The image processing apparatus of claim 17, wherein the first image processing operation excludes a scaling operation and the second image processing operation performs the scaling operation.

19. The image processing apparatus of claim 17, wherein the first image processing operation excludes a demosaicing operation and the second image processing operation performs the demosaicing operation.