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Semiconductor device and electronic appliance

  • US 10,446,103 B2
  • Filed: 01/11/2019
  • Issued: 10/15/2019
  • Est. Priority Date: 09/16/2009
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same conductivity,wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,wherein a gate of the third transistor is electrically connected to a fifth wiring,wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,wherein one of a source and a drain of the fifth transistor is electrically connected to a sixth wiring,wherein other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,wherein a gate of the fifth transistor is electrically connected to the sixth wiring,wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,wherein the second wiring is configured to output a signal, andwherein the sixth wiring is configured to supply a clock signal.

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