Semiconductor device and electronic appliance

• US 10,446,103 B2
• Filed: 01/11/2019
• Issued: 10/15/2019
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Umezaki, Atsushi
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US16/245,324
• Publication Number:
  US 20190237035A1
• Time in Patent Office: 277 Days
• Field of Search: None
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018557 Coupling arrangements; Impedance matching circuits
• CPC Class Codes: H03K 19/018571 of complementary type, e.g. CMOS

Abstract

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Claims

1. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same conductivity,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a sixth wiring,

wherein other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,

wherein a gate of the fifth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the second wiring is configured to output a signal, and

wherein the sixth wiring is configured to supply a clock signal.

2. The semiconductor device according to claim 1, wherein a potential supplied to the fifth wiring and a potential supplied to the sixth wiring are inverted.

3. An electronic appliance comprising the semiconductor device according to claim 1.

4. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a capacitor,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor have the same conductivity,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein a gate of the third transistor is electrically connected to a fifth wiring,

wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a sixth wiring,

wherein other of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor,

wherein a gate of the fifth transistor is electrically connected to the sixth wiring,

wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,

wherein the second wiring is configured to output a signal,

wherein the sixth wiring is configured to supply a clock signal,

wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor, and

wherein a second electrode of the capacitor is electrically connected to the third wiring.

5. The semiconductor device according to claim 4, wherein a potential supplied to the fifth wiring and a potential supplied to the sixth wiring are inverted.

6. An electronic appliance comprising the semiconductor device according to claim 4.