Mixed three-dimensional memory

• US 10,446,193 B2
• Filed: 04/23/2017
• Issued: 10/15/2019
• Est. Priority Date: 04/14/2014
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Zarroli, Michael C
• Application Number:
  US15/494,539
• Publication Number:
  US 20170229158A1
• Time in Patent Office: Days
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H10B 20/367 Gate dielectric programmed, e.g. different thickness
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

The present invention discloses a mixed three-dimensional memory (3D-M_x). It comprises memory arrays (or, memory blocks) of different sizes. In a 3D-M_x with mixed memory blocks, the memory blocks with different sizes are formed side-by-side. In a 3D-M_x with mixed memory arrays, a plurality of small memory arrays are formed side-by-side underneath a single large memory array.

Claims

1. A mixed three-dimensional memory (3D-M_x), comprising:

a first memory block, said first memory block comprising a first plurality of vertically stacked memory levels including a first topmost memory level, said first topmost memory level comprising a first memory array, said first memory array comprising first memory devices, each of said first memory devices sharing at least a first address-line with at least another one of said first memory devices;

a second memory block, said second memory block comprising a second plurality of vertically stacked memory levels including a second topmost level, said second topmost memory level comprising a second memory array, said second memory array comprising second memory devices, each of said second memory devices sharing at least a second address-line with at least another one of said second memory devices;

wherein, said second memory block is located side-by-side with said first memory block;

said first topmost memory level is located at the same physical level with said second topmost memory level; and

, said first memory array is physically larger and comprises more memory devices than said second memory array.

2. The memory according to claim 1, wherein said first memory block stores data.

3. The memory according to claim 2, wherein said data includes digital books, digital maps, digital music, digital movies, and/or digital videos.

4. The memory according to claim 1, wherein said second memory block stores code.

5. The memory according to claim 4, wherein said code includes operating system, software, and/or digital games.

6. A mixed three-dimensional memory (3D-M_x) comprising at least a 3D-M block, said 3D-M block further comprising a plurality of vertically stacked memory levels including a topmost memory level and at least an intermediate memory level, wherein:

said topmost memory level is the topmost memory level among all of said memory levels and comprises a first memory array, said first memory array comprising first memory devices, each of said first memory devices sharing at least a first address-line with at least another one of said first memory devices;

said intermediate memory level is a memory level below said topmost memory level and comprises at least second and third memory arrays, wherein said second memory array comprises second memory devices, each of said second memory devices sharing at least a second address-line with at least another one of said second memory devices;

said third memory array comprises third memory devices, each of said third memory devices sharing at least a third address-line with at least another one of said third memory devices; and

, said second and third memory arrays do not share any memory devices or address-lines;

wherein said first memory array fully covers both said second and third memory arrays; and

, said first memory array is physically larger and comprises more memory devices than said second or third memory array.

7. The memory according to claim 6, wherein said first memory array stores data.

8. The memory according to claim 7, wherein said data include digital books, digital maps, digital music, digital movies, and/or digital videos.

9. The memory according to claim 6, wherein said second or third memory array stores code.

10. The memory according to claim 9, wherein said code includes operating system, software, and/or digital games.