Increasing error rate detection through distribution of read current load

• US 10,446,202 B1
• Filed: 10/28/2016
• Issued: 10/15/2019
• Est. Priority Date: 10/28/2016
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Atsatt, Sean R.
• Primary Examiner(s): Huang, Min
• Application Number:
  US15/338,074
• Time in Patent Office: 1,082 Days
• Field of Search: 713300
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Methods and devices for increasing error detection rate while avoiding excessive power distribution network noise are provided. In one method, memory reads of configuration memory of a first group of sectors of a programmable logic device are performed. The memory reads start at a first start time within a first memory read period. The first memory read period includes an amount of time involved to perform one of the memory reads. The method also includes performing memory reads of configuration memory of a second group of sectors of the programmable logic device. The memory reads of the configuration memory of the second group of sectors start at a second start time within the first memory read period. The second start time is different from the first start time. By offsetting the start times of memory reads, power distribution noise may be reduced.

Claims

1. An integrated circuit device comprising:

a first sector of programmable logic comprising first configuration memory;

a second sector of programmable logic comprising second configuration memory;

a power distribution network that provides power to the first sector of programmable logic and the second sector of programmable logic; and

control circuitry that;

causes a first memory read on the first configuration memory to start at a first time, thereby drawing a first spike of power from the power distribution network around the first time; and

causes a second memory read on the second configuration memory to start at a second time, thereby drawing a second spike of power from the power distribution network around the second time, wherein the first memory read takes place over a first period, and wherein the second time occurs a first offset time from the first time within the first period, such that the first spike of power and the second spike of power are not simultaneous, thereby reducing simultaneous noise or jitter on the power distribution network;

wherein the control circuitry is configured to determine the first time, the first period, the first offset time, or a combination thereof, based at least in part on a voltage level of the power distribution network; and

wherein the control circuitry comprises a device controller that issues;

a global read signal indicating a global read start time to a first sector controller of the first sector of programmable logic and to a second sector controller of the second sector of programmable logic;

a first read offset signal indicating the first time by offset from the global read start time to the first sector controller of the first sector of programmable logic; and

a second read offset signal indicating the second time by offset from the global read start time to the second sector controller of the first sector of programmable logic;

wherein the global read signal and the first read offset signal enable the first sector controller to schedule the first memory read at the first time; and

wherein the global read signal and the second read offset signal enable the second sector controller to schedule the second memory read at the second time.

2. The integrated circuit device of claim 1, comprising a third sector of programmable logic comprising third configuration memory, wherein the control circuitry causes a third memory read on the third configuration memory to start at a third time, and wherein the third time occurs a second offset time from the first time within the first period.

3. The integrated circuit device of claim 1, wherein the first sector controller schedules the first memory read at least in part by:

reading a first current time value of a first internal global timer of the first sector controller;

subtracting the global read start time from the first current time value to obtain a first global start time;

adding an offset value indicated by the first read offset signal to obtain the first time; and

initiating the first memory read at the first time.

4. The integrated circuit device of claim 1, comprising an analog-to-digital converter that generates a digital signal indicative of a condition of the power distribution network, wherein the control circuitry determines the first time, the first period, or the first offset time, or any combination thereof, at least partly in response to the digital signal indicative of the condition of the power distribution network.

5. The integrated circuit device of claim 4, wherein the condition of the power distribution network comprises a noise on the power distribution network, the voltage level of the power distribution network, a peak current drawn on the power distribution network, or any combination thereof.

6. The integrated circuit device of claim 1, comprising:

an analog-to-digital converter that generates a digital signal indicative of a condition of the power distribution network; and

threshold circuitry that generates a control signal indicating that digital signal indicative of the condition of the power distribution network has crossed a threshold value;

wherein the control circuitry determines the first time, the first period, or the first offset time, or any combination thereof, at least partly in response to the control signal.

7. The integrated circuit device of claim 1, wherein the first sector of programmable logic or the second sector of programmable logic, or both, comprise a sensitized circuit that fails when an amount of a noise on the power distribution network exceeds a threshold, and wherein a failure of the sensitized circuit causes the control circuitry to change the first time, the first period, or the first offset time, or any combination thereof, to reduce a likelihood of additional noise on the power distribution network due to the first memory read or the second memory read, or both.

8. The integrated circuit device of claim 1, comprising a device condition sensor that generates a signal indicative of a condition of the integrated circuit device that affects behavior of the power distribution network, wherein the control circuitry determines the first time, the first period, or the first offset time, or any combination thereof, at least partly in response to the signal indicative of the condition of the integrated circuit device.

9. The integrated circuit device of claim 8, wherein the device condition sensor comprises a thermal sensor.

10. A method comprising:

selecting a first sector of a programmable logic device and a second sector of the programmable logic device from among a total number of sectors of the programmable logic device to physically spatially distribute a first memory read of configuration memory of the first sector and a second memory read of configuration memory of the second sector;

performing the first memory read and the second memory read, wherein each of the first memory read and the second memory read starts at a first start time within a first memory read period, and wherein the first memory read period comprises an amount of time involved to perform the first memory read or the second memory read; and

performing a third memory read of configuration memory of a third sector of the programmable logic device, wherein the third memory read starts at a second start time within the first memory read period, and wherein the second start time is different from the first start time.

11. The method of claim 10, wherein the second start time is offset from the first start time at least by an amount of time of a read current pulse width plus an amount of time of a read current settling time.

12. The method of claim 10, wherein the second start time is offset from the first start time at least by an amount of time of a read current pulse width, plus an amount of time of a read current settling time, plus an additional uncertainty time.

13. The method of claim 10, wherein the first sector and the second sector are selected based at least partly on a noise on a power distribution network of the programmable logic device, a voltage level of the power distribution network, a peak current drawn on the power distribution network, thermal feedback of the programmable logic device, or any combination thereof, to prevent an amount of noise or jitter on the power distribution network of the programmable logic device from exceeding an acceptable local level.

14. At least one article of manufacture comprising at least one tangible, non-transitory, machine-readable media comprising instructions to:

receive a circuit design into a processor;

modify the circuit design to physically spatially distribute the circuit design over at least configuration memory of a first sector of an integrated circuit device that the circuit design is programmed into and configuration memory of a second sector of the integrated circuit device to improve read margins; and

modify the circuit design to enable the integrated circuit device to perform error detection on configuration memory of the integrated circuit device at a first rate by offsetting a first start time of a first memory read of the configuration memory of the first sector and a second start time of a second memory read of the configuration memory of the second sector from a third start time of a third memory read of the configuration memory of a third sector of the integrated circuit device within a read period, wherein the first start time and the second start time are the same.

15. The article of manufacture of claim 14, comprising instructions to predict a peak current load of the circuit design that is expected to occur when the circuit design is programmed into the configuration memory of the integrated circuit device.

16. The article of manufacture of claim 14, wherein the instructions cause the circuit design to be modified to generate an indication to control circuitry of the integrated circuit device of a current load on a power distribution network of the integrated circuit device during runtime.

17. The article of manufacture of claim 14, wherein the instructions comprise instructions to calibrate the circuit design by running circuit design on the integrated circuit device at peak current while varying a read rate until a failure is identified, and wherein the first rate is determined based at least in part on the identified failure.