Write cycle execution based on data comparison
First Claim
1. A system comprising:
- a first memory component; and
a processing device, operatively coupled to the first memory component, configured to perform operations comprising;
receiving a request to write a first sequence of data bits from a first data block of a second memory component to the first memory component;
in response to receiving the request, reading a second sequence of data bits from a second data block stored in at the first memory component;
comparing the first sequence of data bits with the second sequence of data bits; and
determining whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the first memory component based on a result of the comparing of the first sequence of data bits with the second sequence of data bits.
5 Assignments
0 Petitions
Accused Products
Abstract
Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits. The processing device determines whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the memory media of the first memory component based on a result of comparing the first sequence of data bits with the second sequence of data bits.
7 Citations
20 Claims
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1. A system comprising:
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a first memory component; and a processing device, operatively coupled to the first memory component, configured to perform operations comprising; receiving a request to write a first sequence of data bits from a first data block of a second memory component to the first memory component; in response to receiving the request, reading a second sequence of data bits from a second data block stored in at the first memory component; comparing the first sequence of data bits with the second sequence of data bits; and determining whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the first memory component based on a result of the comparing of the first sequence of data bits with the second sequence of data bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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receiving, at a media controller operatively coupled to a first memory component, a request to write a first sequence of data bits from a first data block of a second memory component to the first memory component; in response to receiving the request, reading a second sequence of data bits from a second data block stored at the first memory component; comparing, by one or more data comparators of the media controller, the first sequence of data, bits with the second sequence of data bits; and determining, by the media controller, whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the first memory component based on a result of the comparing of the first sequence of data bits with the second sequence of data bits. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A memory sub-system comprising:
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a memory component; and a media controller, operatively coupled to the memory component, the media controller configured to perform operations comprising; receiving a request to write a first sequence of data bits to the memory component; in response to receiving the request, reading a second sequence of data bits from the memory component, the first sequence of data bits corresponding to the second sequence of data bits; and determining whether to execute a write cycle, at the memory component, to write the first sequence of data bits to the memory component based on a comparison of the first sequence of data bits with the second sequence of data bits. - View Dependent Claims (18, 19, 20)
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Specification