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Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

  • US 10,446,210 B2
  • Filed: 12/27/2017
  • Issued: 10/15/2019
  • Est. Priority Date: 09/27/2016
  • Status: Active Grant
First Claim
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1. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

  • an input register operable to receive a first data word and an associated address to be written into a memory bank;

    a pre-read register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address, and wherein the pre-read register is further operable to store mask bits associated with pre-reading the second data word, wherein the mask bits comprise information regarding a bit-wise comparison between the first data word and the second data word; and

    a write register of a second pipe-stage operable to receive the first data word, the associated address and the mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word, wherein the second pipe-stage follows the first pipe-stage.

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