Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers

• US 10,446,210 B2
• Filed: 12/27/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, El-Baraji, Mourad, Crudele, Lester, Hillman, Daniel
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US15/855,707
• Publication Number:
  US 20180122448A1
• Time in Patent Office: 657 Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The memory pipeline also comprises a pre-read register of the first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address. Finally, the memory pipeline comprises a write register of the second pipe-stage operable to receive the first data word, the associated address and mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word.

Claims

1. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

an input register operable to receive a first data word and an associated address to be written into a memory bank;

a pre-read register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address, and wherein the pre-read register is further operable to store mask bits associated with pre-reading the second data word, wherein the mask bits comprise information regarding a bit-wise comparison between the first data word and the second data word; and

a write register of a second pipe-stage operable to receive the first data word, the associated address and the mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word, wherein the second pipe-stage follows the first pipe-stage.

2. The memory pipeline of claim 1, wherein said memory bank comprises memory cells that are spin-transfer torque magnetic random access memory (STT-MRAM) cells.

3. The memory pipeline of claim 1, wherein the pre-read register further comprises ECC bits for correcting bit errors in data words read from the memory bank.

4. The memory pipeline of claim 1, wherein the pre-read is performed as part of a bit redundancy remapping operation.

5. The pipelink bank of claim 1, wherein the pre-read register stores the mask bits in a first level dynamic redundancy register.

6. The memory pipeline of claim 1, further comprising:

a delay register of a third pipe-stage operable to provide delay cycles between the write register and a verify register, wherein the delay cycles are used to find a verify operation in a first level dynamic redundancy register with a row address in common with the first data word wherein the third pipe-stage follows the second pipe-stage.

7. The memory pipeline of claim 6, wherein the delay register is further operable to receive the first data word and associated address from the write register.

8. The memory pipeline of claim 7, wherein the delay register is further operable to transmit the first data word and associated address to the first level dynamic redundancy register responsive to receipt of a row address change signal.

9. The memory pipeline of claim 7, further comprising:

a verify register of a fourth pipe-stage operable to receive the first data word and associated address from the delay register, and further operable to read a third data word at the associated address from the memory bank, wherein the fourth pipe-stage follows the third pipe-stage; and

compare logic operable to compare contents of the first data word and the third data word to determine if the first data word wrote correctly to the memory bank.

10. A system for performing a write operation in a memory device, the system comprising:

a memory pipeline;

a memory bank coupled to the memory pipeline; and

a first level dynamic redundancy register, wherein the memory pipeline comprises;

an input register operable to receive a first data word and an associated address to be written into the memory bank;

a pre-read register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address, and wherein the pre-read register is further operable to store mask bits associated with pre-reading the second data word, wherein the mask bits comprise information regarding a bit-wise comparison between the first data word and the second data word; and

a write register of a second pipe-stage operable to receive the first data word, the associated address and the mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word, wherein the second pipe-stage follows the first pipe-stage.

11. The system of claim 10, wherein said memory bank comprises memory cells that are spin-transfer torque magnetic random access memory (STT-MRAM) cells.

12. The system of claim 10, wherein the pre-read register further comprises ECC bits for correcting bit errors in data words read from the memory bank.

13. The system of claim 10, wherein the pre-read is performed as part of a bit redundancy remapping operation.

14. The system of claim 10, wherein the pre-read register stores the mask bits in the first level dynamic redundancy register.

15. The system of claim 10, further comprising:

a delay register of a third pipe-stage operable to provide delay cycles between the write register and a verify register, wherein the delay cycles are used to find a verify operation in a first level dynamic redundancy register with a row address in common with the first data word wherein the third pipe-stage follows the second pipe-stage.

16. The system of claim 15, wherein the delay register is further operable to receive the first data word and associated address from the write register.

17. The system of claim 16, wherein the delay register is further operable to transmit the first data word and associated address to the first level dynamic redundancy register responsive to receipt of a row address change signal.

18. The system of claim 16, further comprising:

a verify register of a fourth pipe-stage operable to receive the first data word and associated address from the delay register, and further operable to read a third data word at the associated address from the memory bank, wherein the fourth pipe-stage follows the third pipe-stage; and

compare logic operable to compare contents of the first data word and the third data word to determine if the first data word wrote correctly to the memory bank.

19. A memory pipeline for performing a write operation in a memory device, the memory pipeline comprising:

an input register operable to receive a first data word and an associated address to be written into a memory bank, wherein the memory bank comprises memory cells that are spin-transfer torque magnetic random access memory (STT-MRAM) cells;

a pre-read register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register and further operable to pre-read a second data word stored in the memory bank at the associated address, and wherein the pre-read register is further operable to store mask bits associated with pre-reading the second data word, wherein the mask bits comprise information regarding a bit-wise comparison between the first data word and the second data word; and

a write register of a second pipe-stage operable to receive the first data word, the associated address and the mask bits from the pre-read register, wherein the write register is further operable to use information from the mask bits to write the first data word into the memory bank by changing those bits in the first data word that differ from the second data word, wherein the second pipe-stage follows the first pipe-stage.

20. The memory pipeline of claim 19, wherein the pre-read register further comprises ECC bits for correcting bit errors in data words read from the memory bank.