Bitline control in differential magnetic memory

• US 10,446,213 B1
• Filed: 05/16/2018
• Issued: 10/15/2019
• Est. Priority Date: 05/16/2018
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Zhang, Yaojun, Alam, Syed M., Andre, Thomas
• Primary Examiner(s): Le, Toan K
• Application Number:
  US15/980,977
• Time in Patent Office: 517 Days
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits

Abstract

The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.

Claims

1. A magnetoresistive memory, comprising:

a first memory cell that includes;

a first select device;

a first magnetic tunnel junction coupled in series with the first select device;

a second select device; and

a second magnetic tunnel junction coupled in series with the second select device,

wherein the first memory cell is configured to store a single bit by storing complementary states in the first and second magnetic tunnel junctions;

a first access circuit configured to receive access command signals for accessing the first magnetic tunnel junction, wherein the first access circuit includes a first access switch and a second access switch;

a second access circuit configured to receive access command signals for accessing the second magnetic tunnel junction, where the second access circuit includes a third access switch and a fourth access switch; and

a current generating circuit coupled to the first and second magnetic tunnel junctions, wherein, based on data input signals, the current generation circuit is configured to generate (i) a first write current through the first magnetic tunnel junction and (ii) a second write current through the second magnetic tunnel junction based on data input signals.

2. The magnetoresistive memory of claim 1, wherein, during a stand-by mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

3. The magnetoresistive memory of claim 1, wherein, during a boot mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

4. The magnetoresistive memory of claim 1, wherein, when storing a “

1”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a high voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a high voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a low voltage supply.

5. The magnetoresistive memory of claim 1, wherein, when storing a “

0”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a high voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a low voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a high voltage supply.

6. The magnetoresistive memory of claim 1, wherein, when reading a value stored in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, a fifth access switch is configured to couple a second end of the first magnetic tunnel junction to a sense amplifier, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and a sixth access switch is configured to couple a second end of the second magnetic tunnel junction to the sense amplifier.

7. A magnetoresistive memory, comprising:

a first memory cell that includes;

a first select device;

a first magnetic tunnel junction coupled in series with the first select device;

a second select device; and

a second magnetic tunnel junction coupled in series with the second select device, wherein the first memory cell is configured to store a single bit by storing complementary states in the first and second magnetic tunnel junctions;

a first access circuit configured to receive access command signals for accessing the first magnetic tunnel junction, wherein the first access circuit includes a first access switch and a second access switch;

a second access circuit configured to receive access command signals for accessing the second magnetic tunnel junction, wherein the second access circuit includes a third access switch and a fourth access switch, and wherein the first access switch, the second access switch, the third access switch, and the fourth access switch are enabled from masked control signals; and

a current generating circuit coupled to the first and second magnetic tunnel junctions, wherein, based on data input signals, the current generation circuit is configured to generate (i) a first write current through the first magnetic tunnel junction and (ii) a second write current through the second magnetic tunnel junction.

8. The magnetoresistive memory of claim 7, wherein, during a stand-by mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

9. The magnetoresistive memory of claim 7, wherein, during a boot mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

10. The magnetoresistive memory of claim 7, wherein, when storing a “

1”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a high voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a high voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a low voltage supply.

11. The magnetoresistive memory of claim 7, wherein, when storing a “

0”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a high voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a low voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a high voltage supply.

12. The magnetoresistive memory of claim 7, wherein, when reading a value stored in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, a fifth access switch is configured to couple a second end of the first magnetic tunnel junction to a sense amplifier, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and a sixth access switch is configured to couple a second end of the second magnetic tunnel junction to the sense amplifier.

13. A magnetoresistive memory, comprising:

a first memory cell that includes;

a first select device;

a first magnetic tunnel junction coupled in series with the first select device;

a second select device; and

a second magnetic tunnel junction coupled in series with the second select device, wherein the first memory cell is configured to store a single bit by storing complementary states in the first and second magnetic tunnel junctions;

a first access circuit configured to receive access command signals for accessing the first magnetic tunnel junction, wherein the first access circuit includes a first access switch and a second access switch;

a second access circuit configured to receive access command signals for accessing the second magnetic tunnel junction, wherein the second access circuit includes a third access switch and a fourth access switch, and wherein the first access switch, the second access switch, the third access switch, and the fourth access switch are enabled from masked control signals; and

a current generating circuit coupled to the first and second magnetic tunnel junctions, wherein the current generation circuit configured to generate (i) a first write current through the first magnetic tunnel junction and (ii) a second write current through the second magnetic tunnel junction based on data input signals, wherein the data input signals are configured to generate the masked control signals.

14. The magnetoresistive memory of claim 13, wherein, during a stand-by mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

15. The magnetoresistive memory of claim 13, wherein, during a boot mode, the first access switch and the second access switch are configured to couple a first end and a second end of the first magnetic tunnel junction to a low voltage supply, and wherein the third access switch and the fourth access switch are configured to couple a first end and a second end of the second magnetic tunnel junction to a low voltage supply.

16. The magnetoresistive memory of claim 13, wherein, when storing a “

1”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a high voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a high voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a low voltage supply.

17. The magnetoresistive memory of claim 13, wherein, when storing a “

0”

in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a high voltage supply, the second access switch is configured to couple a second end of the first magnetic tunnel junction to a low voltage supply, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and the fourth access switch is configured to couple a second end of the second magnetic tunnel junction to a high voltage supply.

18. The magnetoresistive memory of claim 13, wherein, when reading a value stored in the first memory cell, the first access switch is configured to couple a first end of the first magnetic tunnel junction to a low voltage supply, a fifth access switch is configured to couple a second end of the first magnetic tunnel junction to a sense amplifier, the third access switch is configured to couple a first end of the second magnetic tunnel junction to a low voltage supply, and a sixth access switch is configured to couple a second end of the second magnetic tunnel junction to the sense amplifier.

19. The magnetoresistive memory of claim 13, wherein the command signals and the data input signals are input to an array of logic devices to generate the masked control signals.

20. The magnetoresistive memory of claim 13, wherein the command signals and the data input signals are input to an array of NAND devices and inversion devices to generate the masked control signals.