System and method for adaptively optimized refresh of memory

• US 10,446,215 B1
• Filed: 11/16/2016
• Issued: 10/15/2019
• Est. Priority Date: 11/16/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Hughes, Anne, MacLaren, John, Raghu, Devika
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Paperno, Nicholas A.
• Application Number:
  US15/353,150
• Time in Patent Office: 1,063 Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system and method are provided for system for adaptive refresh of a memory device having multiple integrated circuit chips. A command generation portion generates commands for actuating a plurality of operational tasks on the memory device, including at least read, write, and refresh operations for selectively addressed storage cells of the memory device. A command management portion stores the commands and selects from the commands for timely execution of corresponding operational tasks on the memory device. A refresh management portion coupled to the command generation and command management portions actuates a plurality of refresh operations adaptively interleaved with other operational tasks, such that recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time. The refresh management portion selectively actuates each refresh operation for a chip-based selection of storage cells, whereby the storage cells of a selected chip are refreshed.

Claims

1. A system for adaptive refresh of a memory device having multiple integrated circuit chips, the system comprising:

a command generation portion executable to generate commands for actuating a plurality of operational tasks on the memory device, the operational tasks including at least read, write, and refresh operations for selectively addressed storage cells of the memory device, each chip of the memory device defining a plurality of banks, the storage cells of each bank being organized in a plurality of individually accessible pages;

a command management portion coupled to said command generation portion, said command management portion including;

a command queue unit storing the commands for operational tasks on the memory device awaiting execution; and

,

an execution strategy unit coupled to said command queue unit for selecting the commands stored in said command queue unit for timely execution of corresponding operational tasks on the memory device; and

,

a refresh management portion coupled to said command generation and command management portions for scheduling actuation of a plurality of refresh operations to be adaptively interleaved with other operational tasks, wherein full recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time, said refresh management portion including;

a chip refresh unit executable to selectively actuate each refresh operation for a chip-based selection of storage cells, a refresh request for a selected chip actuating a series of refresh operations to collectively refresh the storage cells of the selected chip, whereby for each refresh request for a selected chip the storage cells in all banks of the selected chip are collectively refreshed by the series of refresh operations exclusive of actuation of other operational tasks directed to the selected chip, and

a bank refresh unit executable to selectively actuate each refresh operation for a bank-based selection of storage cells, whereby the storage cells in a selected bank are refreshed, the bank refresh unit having an enable/disable input controllable by the chip refresh unit, whereby the chip refresh unit can enable and disable the bank refresh unit to adaptively adjust the granularity of the refresh operation of the memory device according to three zones of operation, the zones including;

a first zone in which the bank refresh unit is enabled and a memory-chip-based auto refresh is disabled,

a second zone in which the bank refresh unit is disabled and the memory-chip-based auto refresh is enabled, and

a third zone in which the bank refresh unit is enabled and a memory-chip-based auto refresh is enabled only upon determination that the bank refresh unit is unable to refresh the bank-based selection of storage cells within a required refresh time,

wherein the memory-chip-based auto refresh is executed by the chip refresh unit to maintain the refresh request count relative to an average periodic refresh interval time parameter and refresh time debit/credit information associated therewith for the chip-based selection of storage cells.

2. The system as recited in claim 1, wherein said chip refresh unit selectively actuates a refresh operation for a chip responsive to determination of at least one of first and second states for the chip, the chip in the first state having exhausted all refresh deferral options available therefor within the predetermined refresh window, the chip in the second state remaining available to deferral of a refresh operation therefor.

3. The system as recited in claim 2, wherein:

said chip refresh unit is configured to adaptively maintain for each selectable chip of the memory device;

a refresh priority parameter indicative of a refresh deferral history for the selectable chip within the predetermined refresh window; and

,

an activity state parameter indicative of access to the selectable chip by a current or scheduled command for an operational task to be executed within a predefined period of pendency;

said chip refresh unit thereby adaptively scheduling actuation of refresh operations for chips remaining idle during the predefined period of pendency, whereby the storage cells in all banks of a selected idle chip are refreshed exclusive of actuation of other operational tasks directed to the selected chip, and

said chip refresh unit thereby inhibiting refresh operations for chips undergoing an active operational task during the predefined period of pendency.

4. The system as recited in claim 2, wherein said chip refresh unit includes:

a refresh monitoring section for each selectable chip of the memory device, said refresh monitoring section maintaining a refresh deferral history for the selectable chip within the predetermined refresh window; and

,

a refresh control section coupled to each said refresh monitoring section of each selectable chip, said refresh control section generating a refresh request for at least one of the selectable chips responsive to the refresh deferral histories of the selectable chips and activity states of the selectable chips with respect to execution of an operational task thereon within a predefined period of pendency.

5. The system as recited in claim 4, wherein said refresh control section of said chip refresh unit includes a state machine coupled to each said refresh monitoring section and to said command queue and execution strategy units, said state machine determining the selectable chips to be accessed by at least one command in said execution strategy unit or by at least one command in said command queue unit within said predefined period of pendency, said predefined period of pendency indicating a corresponding number of successive commands most imminently awaiting execution.

6. The system as recited in claim 4, wherein said chip refresh unit maintains for each of the selectable chips a refresh priority parameter updated in value according to the refresh deferral history of the selectable chip, said refresh control section generating an override refresh request for a selectable chip responsive to said refresh priority parameter indicating a high priority refresh condition therefor, the override refresh request when generated for a selectable chip overriding the activity state thereof.

7. The system as recited in claim 6, wherein each said refresh monitoring section maintains for at least one of the selectable chips:

a request count indicating a number of deferred refresh operations relative to an average periodic interval, the average periodic interval indicating the frequency of refresh operations required for full refresh of the memory device within the predetermined refresh window;

a timer for a refresh cycle time corresponding to the predetermined refresh window, the refresh cycle time representing a required recovery for the selectable chip following a refresh operation thereon; and

,

an indication of refresh state within the predetermined refresh window for each of the banks in the selectable chip.

8. The system as recited in claim 7, wherein:

the memory device is configured with a stacked device structure having at least one chip stack, each including a plurality of selectable chip levels; and

,

said refresh monitoring section additionally maintains for each of the chip stacks a timer for enforcing a predetermined minimum delay between successive refresh requests for the selectable chip levels of the same chip stack.

9. The system as recited in claim 7, wherein said request count for a selectable chip is incremented with expiration of each average periodic interval without execution of a refresh operation for the selectable chip, and decremented upon each execution of a refresh operation for the selectable chip.

10. A method for adaptive refresh of a memory device having multiple integrated circuit chips, the method comprising:

defining a plurality of banks in each chip of the memory device, each bank being organized into a plurality of individually accessible pages, each page formed by a plurality of storage cells;

executing a command generation portion implemented in a processor to generate commands for actuating a plurality of operational tasks on the memory device, the operational tasks including at least read, write, and refresh operations for selectively addressed storage cells of the memory device;

executing command management on a command management portion implemented in a processor, said command management including;

storing the commands for operational tasks on the memory device in a computer readable command queue unit to await execution; and

,

actuating an execution strategy unit coupled to said command queue unit to select the commands stored in said command queue unit for timely execution of corresponding operational tasks on the memory device; and

,

executing refresh management on a refresh management portion implemented in a processor for scheduling actuation of a plurality of refresh operations to be adaptively interleaved with other operational tasks, wherein full recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time, said refresh management including a per-chip refresh executable to selectively actuate each refresh operation for a chip-based selection of storage cells, a refresh request for a selected chip actuating a series of refresh operations to collectively refresh the storage cells of the selected chip or bank(s), whereby for each refresh request for a selected chip, the storage cells in all banks of the selected chip are collectively refreshed by the series of refresh operations exclusive of actuation of other operational tasks directed to the selected chip, and

said refresh management further including a bank refresh executable to selectively actuate each refresh operation for a bank-based selection of storage cells, whereby the storage cells in a selected bank are refreshed, the bank refresh being enablable/disableable to enable or disable the bank refresh to adaptively adjust the granularity of the refresh operation of the memory device according to three zones of operation, the zones including;

a first zone in which the bank refresh is enabled and a memory-chip-based auto refresh is disabled,

a second zone in which the bank refresh is disabled and the memory-chip-based auto refresh is enabled, and

a third zone in which the bank refresh is enabled and a memory-chip-based auto refresh is enabled only upon determination that the bank refresh unit is unable to refresh the bank-based selection of storage cells within a required refresh time,

wherein, when the memory-chip-based auto refresh is enabled, the per-chip refresh includes the memory-chip-based auto refresh to maintain the refresh request count relative to an average periodic refresh interval time parameter and refresh time debit/credit information associated therewith for the chip-based selection of storage cells.

11. The method as recited in claim 10, wherein said per-chip refresh selectively actuates a refresh operation for a chip responsive to determination of at least one of first and second states for the chip, the chip in the first state having exhausted all refresh deferral options available therefor within the predetermined refresh window, the chip in the second state remaining available to deferral of a refresh operation therefor.

12. The method as recited in claim 11, wherein:

said per-chip refresh adaptively maintains for each selectable chip of the memory device;

a refresh priority parameter indicative of a refresh deferral history for the selectable chip within the predetermined refresh window; and

,

an activity state parameter indicative of access to the selectable chip by a current or scheduled command for an operational task to be executed within a predefined period of pendency;

said per-chip refresh thereby adaptively scheduling actuation of refresh operations for chips remaining idle during the predefined period of pendency, whereby the storage cells in all banks of a selected idle chip are refreshed exclusive of actuation of other operational tasks directed to the selected chip, and

said per-chip refresh thereby inhibiting refresh operations for chips undergoing an active operational task during the predefined period of pendency.

13. The method as recited in claim 11, wherein said per-chip refresh includes:

executing refresh monitoring for each selectable chip of the memory device, said refresh monitoring maintaining a refresh deferral history for the selectable chip within the predetermined refresh window; and

,

executing refresh control for generating a refresh request for at least one of the selectable chips responsive to the refresh deferral histories and activity states of the selectable chips with respect to execution of an operational task thereon within a predefined period of pendency.

14. The method as recited in claim 13, wherein said refresh control includes executing a state machine coupled to said command queue and execution strategy units, and thereby determining the selectable chips to be accessed by at least one command in said execution strategy or command queue units within said predefined period of pendency, said predefined period of pendency indicating a corresponding number of successive commands most imminently awaiting execution.

15. The method as recited in claim 13, wherein said per-chip refresh includes maintaining for each of the selectable chips a refresh priority parameter updated in value according to the refresh deferral history of the selectable chip, said refresh control generating an override refresh request for a selectable chip responsive to said refresh priority parameter indicating a high priority refresh condition therefor, the override refresh request when generated for a selectable chip overriding the activity state thereof.

16. The method as recited in claim 15, wherein:

said refresh monitoring maintains for at least one of the selectable chips;

a request count indicating a number of deferred refresh operations relative to an average periodic interval, the average periodic interval indicating the frequency of refresh operations required for full refresh of the memory device within the predetermined refresh window;

a timer for a refresh cycle time corresponding to the predetermined refresh window, the refresh cycle time representing a required recovery for the selectable chip following a refresh operation thereon; and

,

an indication of refresh state within the predetermined refresh window for each of the banks in the selectable chip; and

,

said request count for a selectable chip is incremented with expiration of each average periodic interval without execution of a refresh operation for the selectable chip, and decremented upon each execution of a refresh operation for the selectable chip.

17. The method as recited in claim 16, wherein:

the memory device is configured with a stacked device structure having at least one chip stack, each including a plurality of selectable chip levels; and

,

said refresh monitoring section additionally maintains for each of the chip stacks a timer for enforcing a predetermined minimum delay between successive refresh requests for the selectable chip levels of the same chip stack.

18. A system for adaptive refresh of a memory device having multiple integrated circuit chips with selective granularity of refresh, the system comprising:

a command generation portion executable to generate commands for actuating a plurality of operational tasks on the memory device, the operational tasks including at least read, write, and refresh operations for selectively addressed storage cells of the memory device, each chip of the memory device defining at least one logical rank containing a plurality of banks, each bank being organized into a plurality of individually accessible pages, each page formed by at least one row of storage cells;

a command management portion coupled to said command generation portion, said command management portion including;

a command queue unit storing the commands for operational tasks on the memory device awaiting execution; and

,

an execution strategy unit coupled to said command queue unit for selecting the commands stored in said command queue unit for timely execution of corresponding operational tasks on the memory device; and

,

a refresh management portion coupled to said command generation and command management portions for scheduling actuation of a plurality of refresh operations to be adaptively interleaved with other operational tasks, wherein full recursive refresh of the storage cells is carried out for the memory device within a predetermined refresh window of time, said refresh management portion including;

a bank refresh unit executable to selectively actuate each refresh operation for a bank-based selection of storage cells, whereby the storage cells in a selected bank are refreshed, the bank refresh unit having an enable/disable input, whereby the bank refresh unit can be enabled or disabled to adaptively adjust the granularity of the refresh operation of the memory device according to three zones of operation, the zones including;

a first zone in which the bank refresh unit is enabled and a memory-chip-based auto refresh is disabled,

a second zone in which the bank refresh unit is disabled and the memory-chip-based auto refresh is enabled, and

a third zone in which the bank refresh unit is enabled and a memory-chip-based auto refresh is enabled only upon determination that the bank refresh unit is unable to refresh the bank-based selection of storage cells within a required refresh time,

wherein the memory-chip-based auto refresh is executed to maintain the refresh request count relative to an average periodic refresh interval time parameter and refresh time debit/credit information associated therewith for the chip-based selection of storage cells; and

,

a rank refresh unit executable to selectively actuate each refresh operation for a rank-based selection of storage cells, a refresh request for a selected rank actuating a series of refresh operations to collectively refresh the storage cells of the selected rank, whereby, for each refresh request for a selected rank, the storage cells in all banks of the selected rank are collectively refreshed by the series of refresh operations exclusive of actuation, between individual refresh operations in the series for the selected rank, of other operational tasks directed to the selected rank and at least one rank other than the selected rank is scheduled to undergo at least one active operational task between individual refresh operations in the series for the selected rank, said rank refresh unit including;

a refresh monitoring section for each selectable rank of the memory device, said refresh monitoring section maintaining a refresh deferral history for the selectable rank within the predetermined refresh window; and

,

a refresh control section coupled to each said refresh monitoring section of each selectable rank, said refresh control section generating a refresh request for at least one of the selectable ranks responsive to the refresh deferral histories and activity states of the selectable ranks with respect to execution of an operational task thereon within a predefined period of pendency.

19. The system as recited in claim 18, wherein:

said refresh control section of said rank refresh unit includes a state machine coupled to each said refresh monitoring section and to said command queue and execution strategy units, said state machine determining the selectable ranks to be accessed by at least one command in said execution strategy unit or by at least one command in said command queue unit within said predefined period of pendency, said predefined period of pendency indicating a corresponding number of successive commands most imminently awaiting execution; and

,

said refresh control section selectively actuates a refresh operation for a rank responsive to determination of at least one of first and second states for the rank, the rank in the first state having exhausted all refresh deferral options available therefor within the predetermined refresh window, the rank in the second state being free of pending access to any bank thereof for execution of an operational task.

20. The system as recited in claim 18, wherein:

said rank refresh unit is configured to adaptively maintain for each selectable rank of the memory device;

a refresh priority parameter indicative of a refresh deferral history for the selectable rank within the predetermined refresh window; and

,

an activity state parameter indicative of access to the selectable chip by a current or scheduled command for an operational task to be executed within a predefined period of pendency;

said rank refresh unit thereby adaptively scheduling actuation of refresh operations for rank remaining idle during the predefined period of pendency, whereby the storage cells in all banks of a selected idle chip are refreshed exclusive of actuation of other operational tasks directed to the selected chip,

said rank refresh unit thereby inhibiting refresh operations for ranks undergoing an active operational task during the predefined period of pendency;

said refresh control section generates an override refresh request for a selectable rank responsive to said refresh priority parameter indicating a high priority refresh condition therefor, the override refresh request when generated for a selectable rank overriding the activity state thereof; and

,

refresh monitoring section maintains a request count indicating a number of deferred refresh operations relative to an average periodic interval, the average periodic interval indicating the frequency of refresh operations required for full refresh of the memory device within the predetermined refresh window, said request count being incremented with expiration of each average periodic interval without execution of a refresh operation for the selectable rank, and decremented upon each execution of a refresh operation for the selectable rank.