Memory device and methods for controlling a memory assist function

• US 10,446,219 B2
• Filed: 12/20/2017
• Issued: 10/15/2019
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gupta, Siddharth, Lehmann, Gunther
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/847,972
• Publication Number:
  US 20180174640A1
• Time in Patent Office: 664 Days
• Field of Search: 365154, 36518905
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

According to one embodiment, a memory device is described including a memory array including a plurality of memory cells wherein each memory cell is coupled to a control line, a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line, a signal generator configured to generate a signal representing at least one of a process corner of the memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device, a signal processing circuit configured to amplify the signal and a controller configured to activate the memory assist circuit based the amplified signal.

Claims

1. A memory device comprising:

a memory array comprising a plurality of memory cells wherein each memory cell is coupled to a control line;

a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line;

a signal generator configured to generate a first signal representing a process corner of the memory device;

a signal processing circuit configured to amplify the first signal; and

a controller configured to activate the memory assist circuit based on the amplified first signal.

2. The memory device of claim 1, wherein the signal represents a combination of the process corner of the memory device, and at least one of a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device.

3. The memory device of claim 1, wherein the memory device comprises a second signal generator configured to generate a second signal representing at least a different one of a process corner of the memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device than the first signal, wherein the memory device comprises a second signal processing circuit configured to amplify the second signal and wherein the controller is configured to activate the memory assist circuit based on the amplified first signal and the amplified second signal.

4. The memory device of claim 1, wherein the signal processing circuit is further configured to digitize the amplified signal and the controller is configured to activate the memory assist circuit based on the digitized amplified signal.

5. The memory device of claim 1, wherein the signal generator comprises a temperature sensor and wherein the signal represents a temperature of the memory device.

6. The memory device of claim 1, wherein the memory cells comprise transistors and the signal generator comprises a plurality of reference transistors and is configured to generate the signal to represent an aging of the memory device based on a behavior of the reference transistors.

7. The memory device of claim 1, wherein the memory cells comprise transistors and the signal generator comprises a plurality of reference transistors and is configured to generate the signal to represent a process corner of the memory device based on a behavior of the reference transistors.

8. The memory device of claim 1, wherein the process corner includes at least one of a process corner of n channel field effect transistors of the memory device and a process corner of p channel field effect transistors of the memory device.

9. The memory device of claim 1, wherein the memory assist circuit is configured to limit a voltage of the control line when the control line is activated.

10. The memory device of claim 1, wherein the control line is a word line or a bit line.

11. The memory device of claim 1, wherein the control line is a word line and the memory assist circuit is a stability assist circuit.

12. The memory device of claim 1, wherein the control line is a bit line and the memory assist circuit is a writability assist circuit.

13. The memory device of claim 1, wherein each memory cell is coupled to a word line and a bit line.

14. The memory device of claim 1, wherein the supply voltage is a supply voltage of the memory array.

15. The memory device of claim 1, wherein the supply voltage is a supply voltage of the memory array based on which the control line is powered when the control line is activated.

16. The memory device of claim 1, wherein the supply voltage is a high supply potential of the memory array.

17. The memory device of claim 1, wherein the amplified first signal represents a digital value and the controller is configured to activate the memory assist circuit based on a comparison of the digital value with a predetermined threshold.

18. A method for controlling a memory assist function comprising:

generating a signal representing at least one of a process corner of a memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device;

amplifying the signal;

digitizing the amplified signal;

activating, a memory assist circuit, based on the digitized amplified signal; and

applying, by the memory assist circuit when activated, a reduction of a voltage of a control line to which each of a plurality of memory cells of a memory array of the memory device is coupled based on the amplified signal.

19. A memory device comprising:

a memory array comprising a plurality of memory cells wherein each memory cell is coupled to a control line;

a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line;

a signal generator configured to generate a first signal representing at least one of a process corner of the memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device;

a signal processing circuit configured to amplify the first signal; and

a controller configured to activate the memory assist,

wherein the amplified first signal represents a digital value and the controller is further configured to activate the memory assist circuit based on a comparison of the digital value with a predetermined threshold.

20. A memory device comprising:

a memory array comprising a plurality of memory cells wherein each memory cell is coupled to a control line;

a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line;

a signal generator configured to generate a first signal representing at least one of a process corner of the memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device;

a signal processing circuit configured to amplify the first signal; and

a controller configured to activate the memory assist circuit based on the amplified first signal,

wherein the signal processing circuit is further configured to digitize the amplified first signal and the controller is configured to activate the memory assist circuit based on the digitized amplified first signal.