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Memory device and methods for controlling a memory assist function

  • US 10,446,219 B2
  • Filed: 12/20/2017
  • Issued: 10/15/2019
  • Est. Priority Date: 12/20/2016
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a memory array comprising a plurality of memory cells wherein each memory cell is coupled to a control line;

    a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line;

    a signal generator configured to generate a first signal representing a process corner of the memory device;

    a signal processing circuit configured to amplify the first signal; and

    a controller configured to activate the memory assist circuit based on the amplified first signal.

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