Sense amplifier with lower offset and increased speed
First Claim
1. A method, comprising:
- configuring an amplifier component to operate in an amplifier mode during a first pre-charging portion of a read operation based at least in part on activating or deactivating a second switching component in the amplifier component;
coupling, while the amplifier component is operating in the amplifier mode, a first voltage source with a first input of the amplifier component, a first output of the amplifier component with a second input of the amplifier component, and the first output of the amplifier component with a digit line to pre-charge the digit line to a first voltage during the first pre-charging portion of the read operation;
coupling, during a signal development portion of the read operation of a memory cell, a ferroelectric capacitor of the memory cell with the digit line associated with the memory cell to adjust an amount of electric charge on the digit line;
coupling, during the signal development portion, the first input of the amplifier component with the digit line to amplify a voltage of the digit line;
decoupling, after the signal development portion of the read operation, the first input of the amplifier component from the digit line;
configuring the amplifier component to operate in a latch mode based at least in part on activating or deactivating a first switching component in the amplifier component; and
outputting, on the first output of the amplifier component, a state of the memory cell while the amplifier component operates in the latch mode, wherein the first pre-charging portion of the read operation occurs before the signal development portion of the read operation.
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Accused Products
Abstract
Methods and apparatus for sensing a memory cell using lower offset, higher speed sense amplifiers are described. A sense amplifier may include an amplifier component that is configurable to operate in an amplifier mode or a latch mode. In some examples, the amplifier component may be configured to operate in the amplifier or latch mode by activating or deactivating switching components inside the amplifier component. When configured to operate in the amplifier mode, the amplifier component may be used, during a read operation of a memory cell, to pre-charge a digit line and/or amplify a signal received from the memory cell. When configured to operate in the latch mode, the amplifier component may be used to latch a state of the memory cell. In some cases, the amplifier component may use some of the same internal circuitry for pre-charging the digit line, amplifying the signal, and/or latching the state.
15 Citations
22 Claims
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1. A method, comprising:
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configuring an amplifier component to operate in an amplifier mode during a first pre-charging portion of a read operation based at least in part on activating or deactivating a second switching component in the amplifier component; coupling, while the amplifier component is operating in the amplifier mode, a first voltage source with a first input of the amplifier component, a first output of the amplifier component with a second input of the amplifier component, and the first output of the amplifier component with a digit line to pre-charge the digit line to a first voltage during the first pre-charging portion of the read operation; coupling, during a signal development portion of the read operation of a memory cell, a ferroelectric capacitor of the memory cell with the digit line associated with the memory cell to adjust an amount of electric charge on the digit line; coupling, during the signal development portion, the first input of the amplifier component with the digit line to amplify a voltage of the digit line; decoupling, after the signal development portion of the read operation, the first input of the amplifier component from the digit line; configuring the amplifier component to operate in a latch mode based at least in part on activating or deactivating a first switching component in the amplifier component; and outputting, on the first output of the amplifier component, a state of the memory cell while the amplifier component operates in the latch mode, wherein the first pre-charging portion of the read operation occurs before the signal development portion of the read operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus, comprising:
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an amplifier capacitor coupled with a digit line associated with a memory cell; and an amplifier component configured to be selectively coupled with the digit line and with the amplifier capacitor, the amplifier component comprising; a plurality of transistors, and a plurality of switching components configured to select a mode of the amplifier component by activating one or more electrical connections between respective transistors, the plurality of switching components configured to select the mode as an amplifier mode that configures the amplifier component to, while an input of the amplifier component is coupled with the digit line and an output of the amplifier component is coupled with the amplifier capacitor, adjust a voltage of the amplifier capacitor, and the plurality of switching components configured to select the mode as a latch mode that configures the amplifier component to latch a state of the memory cell in response to an activation signal, wherein the plurality of switching components are configured to select the mode as the amplifier mode which configures a first transistor of the plurality of transistors and a second transistor of the plurality of transistors to operate in a current mirror mode by activating an electrical connection between a gate of the first transistor and a gate of the second transistor. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A memory device, comprising:
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a memory cell; a digit line configured to be selectively coupled with the memory cell; an amplifier component configured to be selectively coupled with the digit line; a controller to; couple, during a first portion of a read operation of the memory cell, the amplifier component to the digit line; couple, during the first portion, a ferroelectric capacitor of the memory cell with the digit line to adjust an amount of electric charge on the digit line; decouple the amplifier component from the digit line after the first portion of the read operation; configure the amplifier component to operate in a latch mode based at least in part on configuring a plurality of switching components in the amplifier component; cause a state of the memory cell to be latched while the amplifier component is configured to operate in the latch mode; configure the amplifier component to operate in an amplifier mode during a second portion of the read operation based at least in part on configuring the plurality of switching components in the amplifier component; and couple, while the amplifier component is operating in the amplifier mode, a first input of the amplifier component with a second voltage source and an output of the amplifier component with the digit line to pre-charge the digit line to a first voltage during the second portion of the read operation, wherein the second portion of the read operation occurs before the first portion of the read operation. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification