Adjusting voltage on adjacent word line during verify of memory cells on selected word line in multi-pass programming

• US 10,446,244 B1
• Filed: 04/09/2018
• Issued: 10/15/2019
• Est. Priority Date: 04/09/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Diep, Vinh, Lu, Ching-Huang, Zhang, Zhengyi, Dong, Yingda
• Primary Examiner(s): Le, Toan K
• Application Number:
  US15/948,761
• Publication Number:
  US 20190311772A1
• Time in Patent Office: 554 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.

Claims

1. An apparatus, comprising:

a set of memory cells arranged in NAND strings and connected to a plurality of word lines, the plurality of word lines comprising a selected word line and unselected word lines; and

a control circuit, the control circuit to perform verify tests for memory cells connected to the selected word line in one program loop, is configured to apply a plurality of verify voltages in turn to the selected word line, and during the application of each verify voltage, sense a conductive level of the memory cells connected to the selected word line and apply a variable voltage to a first adjacent word line of the selected word line, wherein the variable voltage is a first increasing function of the verify voltages.

2. The apparatus of claim 1, wherein:

for each of the verify voltages, a difference by which the variable voltage exceeds the verify voltage is a constant.

3. The apparatus of claim 1, wherein:

for each of the verify voltages, a difference by which the variable voltage exceeds the verify voltage decreases as the verify voltage increases.

4. The apparatus of claim 1, wherein:

the variable voltages range from a lowest level to a highest level;

the control circuit is configured to apply another voltage to a second adjacent word line of the selected word line during the application of each verify voltage; and

the another voltage is equal to the highest level.

5. The apparatus of claim 1, wherein:

memory cells connected to the first adjacent word line are in at least two different threshold voltage distributions during the verify tests for the memory cells connected to the selected word line.

6. The apparatus of claim 1, wherein:

the verify tests are performed in a final pass of a multi-pass program operation which uses a back and forth word line programming order; and

the first adjacent word line is programmed after the selected word line in each pass of the multi-pass program operation.

7. The apparatus of claim 6, wherein:

the multi-pass program operation comprises a next to last pass for the selected word line; and

the control circuit, to perform verify tests for the memory cells connected to the selected word line in a program loop in the next to last pass, is configured to apply a plurality of verify voltages in turn to the selected word line, and during the application of each verify voltage, sense a conductive level of the memory cells connected to the selected word line and apply a fixed voltage to the first adjacent word line.

8. The apparatus of claim 6, wherein:

the multi-pass program operation comprises a first pass for the selected word line in which the memory cells of the selected word line are kept in an erased state or programmed to an intermediate state, followed by a first pass for the first adjacent word line in which memory cells of the first adjacent word line are kept in the erased state or programmed to the intermediate state, followed by a second pass for the selected word line in which the memory cells of the selected word line are programmed from the erased state and the intermediate state to final states, followed by a second pass for the first adjacent word line in which the memory cells of the first adjacent word line are programmed from the erased state and the intermediate state to the final states.

9. The apparatus of claim 6, wherein:

the multi-pass program operation comprises a first pass for the selected word line in which the memory cells of the selected word line are programmed to offset voltages below final states, followed by a first pass for the first adjacent word line in which memory cells of the first adjacent word line are programmed to the offset voltages below the final states, followed by a second pass for the selected word line in which the memory cells of the selected word line are programmed from the offset voltages to the final states, followed by a second pass for the first adjacent word line in which the memory cells of the first adjacent word line are programmed from the offset voltages to the final states.

10. The apparatus of claim 1, wherein:

in the program loop, a number of the verify voltages is more than a number of different levels of the variable voltages.

11. The apparatus of claim 1, wherein:

the verify voltages comprise a lowest level, a next to lowest level, a next to highest level and a highest level;

the variable voltages comprise a lowest level, a next to lowest level and a highest level;

the lowest level of the variable voltages is applied to the first adjacent word line when the lowest level of the verify voltages is applied to the selected word line;

the next to lowest level of the variable voltages is applied to the first adjacent word line when the next to lowest level of the verify voltages is applied to the selected word line; and

the highest level of the variable voltages is applied to the first adjacent word line when the next to highest level and the highest level of the verify voltages are applied to the selected word line.

12. The apparatus of claim 1, wherein:

the control circuit is configured to set the variable voltages as a decreasing function of a number of program-erase cycles of the set of memory cells.

13. A method, comprising:

applying verify voltage signal to memory cells connected to a selected word line; and

during the applying of the verify voltage signal, sensing the memory cells connected to the selected word line and applying a voltage signal to a first adjacent word line of the selected word line, wherein the voltage signal applied to the first adjacent word line exceeds the verify voltage signal and steps up as the verify voltage signal steps up.

14. The method of claim 13, further comprising:

during the applying of the verify voltage signal, applying a voltage signal to a second adjacent word line of the selected word line, wherein the voltage signal applied to the second adjacent word line is fixed as the verify voltage signal steps up.

15. The method of claim 13, wherein:

the verify voltage signal is applied in a final pass of a multi-pass program operation for the selected word line which uses a back and forth word line programming order;

the first adjacent word line is programmed after the selected word line in each pass of the multi-pass program operation; and

the first adjacent word line is partly but not fully programmed when the verify voltage signal is applied to the selected word line.

16. The method of claim 13, wherein:

a number of levels in the verify voltage signal is more than a number of levels of the voltage signal applied to the first adjacent word line.

17. An apparatus, comprising:

a set of memory cells arranged in a NAND string, the set of memory cells comprising a selected memory cell and an adjacent memory cell;

means for applying different verify voltages to the selected memory cell during verify tests of a program loop; and

means for applying different voltages to the adjacent memory cell during the verify tests, when the different verify voltages are applied to the selected memory cell.

18. The apparatus of claim 17, wherein:

the different voltages applied to the adjacent memory cell exceed the different verify voltages applied to the selected memory cell by a fixed amount.

19. The apparatus of claim 17, wherein:

the different voltages applied to the adjacent memory cell exceed the different verify voltages applied to the selected memory cell by varying amounts.

20. The apparatus of claim 17, further comprising:

means for applying a fixed voltage to another adjacent memory cell of the selected memory cell during the verify tests.