Non-volatile memory array with memory gate line and source line scrambling

• US 10,446,245 B2
• Filed: 12/20/2018
• Issued: 10/15/2019
• Est. Priority Date: 12/08/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Chen, Chun, Betser, Yoram, Chang, Kuo Tung, Givant, Amichai, Shetty, Shivananda, Fang, Shenqing
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US16/227,015
• Publication Number:
  US 20190198124A1
• Time in Patent Office: 299 Days
• Field of Search: 36518517, 36518501
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Claims

1. A method, comprising:

providing a non-volatile memory (NVM) array, wherein the non-volatile memory array includes at least four non-volatile memory (NVM) cells coupled in a same column of the NVM array, wherein each NVM cell includes a memory gate and a select gate, wherein first and second NVM cells of the at least four NVM cells share a first source line, and third and fourth NVM cells share a second source line;

coupling the first source line to a first common electrical node to form a first source line group, wherein the first source line group includes at least another source line of the same column that is not adjacent to the first source line;

coupling the second source line to a second common electrical node to form a second source line group, wherein the second source line group includes at least another source line of the same column that is not adjacent to the second source line; and

selecting the first NVM cell for a program operation while deselecting the second NVM cell for the program operation, comprising;

coupling a high program voltage to a first memory gate of the first NVM cell and a low inhibit voltage to a second memory gate of the second NVM cell; and

coupling two different source voltages to the first and second source line groups.

2. The method of claim 1, wherein the two different source voltages are provided from two different source line driver circuits.

3. The method of claim 1, further comprising:

coupling a high select voltage to a first select gate of the first NVM cell to select the first NVM cell for the program operation.

4. The method of claim 1, further comprising:

coupling a low select voltage to a second select gate of the second NVM cell to deselect the second NVM cell for the program operation.

5. The method of claim 1, wherein the memory gates of the second and third NVM cells are electrically connected, and wherein the first and second source lines are physically adjacent to one another.

6. The method of claim 1, wherein the second memory gate of the second NVM cell and a third memory gate of the third NVM cell are electrically connected.

7. The method of claim 1, wherein the first and second source lines are physically adjacent to one another.

8. The method of claim 1, further comprising:

coupling a high source voltage to the first source line group and a low source voltage to the second source line group.

9. The method of claim 1, further comprising:

electrically coupling the second and a third memory gates to receive a same voltage.

10. The method of claim 1, wherein the high program voltage is in an approximate range of 5 V to 10 V, and the low inhibit voltage in an approximate range of 0 V to 5 V.

11. A method of operating a memory array, comprising:

obtaining the memory array comprising non-volatile memory (NVM) cells, each including a memory gate and a select gate, arranged in rows and columns, wherein;

two adjacent NVM cells of a same column that share a source region form an NVM pair, and wherein multiple NVM pairs are coupled to one another in the same column;

at least two memory gates of NVM cells of a same row share a memory gate line;

at least two source regions of NVM cells of the same row share a source line; and

configuring a source line connection routing that provides multiple common electrical nodes to form at least two source line groups, further comprising;

selecting multiple source lines to form a source line group, wherein the multiple source lines in the source line group are not physically adjacent to one another;

forming multiple source line groups; and

coupling each of the multiple common electrical node to one of the multiple source line groups to receive a same voltage signal.

12. The method of claim 11, wherein:

at least two select gates of NVM cells of the same row share a select gate line; and

at least two drain regions of NVM cells of the same column share a bit line, wherein the drain region of each of the NVM cells is disposed adjacent to the select gate.

13. The method of claim 11, further comprising:

coupling each of the multiple source line groups to a separate source line driver circuit, wherein each of the multiple source line groups is configured to receive a separate source voltage.

14. The method of claim 11, further comprising:

configuring a memory gate connection routing, comprising;

selecting multiple memory gate lines to form a memory gate line group, wherein NVM cells associated with the multiple memory gate lines in a same memory gate line group do not share any source line;

forming multiple memory gate line groups; and

electrically connecting each of the multiple memory gate line groups to a separate memory gate line driver circuit, configured to provide a separate memory gate voltage.

15. The method of claim 11, the memory array comprising 2N rows of NVM cells, N being a natural number, wherein:

multiple odd source lines including 1^st to (N−

1)^th source lines are connected electrically by a first source line connection routing;

multiple even source lines including 0^th to (N−

2)^th source lines are connected electrically by a second source line connection routing; and

the first and second source line connection routings are coupled to two different source line driver circuits.

16. The method of claim 11, the memory array comprising 2N rows of NVM cells, N being a natural number, wherein:

0^th and (2N−

1)^th memory gate lines are connected electrically by a first memory gate line connection routing;

at least one remaining odd memory gate line is connected electrically to its adjacent even memory gate line by a second memory gate line connection routing; and

the first and the second memory gate line connection routing are each coupled to a separate memory gate driver circuit.

17. The method of claim 14, wherein the memory gate connection routing includes metal 1 (M1) connection to the memory gate driver circuit.

18. The method of claim 11, wherein the NVM cells include two-transistor memory cells.

19. The method of claim 11, wherein the NVM cells include split gate memory cells.