Semiconductor memory device capable of shortening erase time
First Claim
1. A semiconductor memory device comprising:
- a memory cell array including memory cells, the memory cells arranged in the memory cell array in a matrix form, and the memory cells connected to word lines and bit lines;
a control circuit configured to control voltages of the word lines and the bit lines,wherein, in a read operation for a first memory cell among the memory cells, the control circuit applies a first voltage to a first word line among the word lines, the first word line connected to the first memory cell, andthe control circuit applies a second voltage lower than the first voltage to the first word line to read a data of the first memory cell.
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Accused Products
Abstract
In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≤n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
16 Citations
5 Claims
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1. A semiconductor memory device comprising:
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a memory cell array including memory cells, the memory cells arranged in the memory cell array in a matrix form, and the memory cells connected to word lines and bit lines; a control circuit configured to control voltages of the word lines and the bit lines, wherein, in a read operation for a first memory cell among the memory cells, the control circuit applies a first voltage to a first word line among the word lines, the first word line connected to the first memory cell, and the control circuit applies a second voltage lower than the first voltage to the first word line to read a data of the first memory cell. - View Dependent Claims (2, 3, 4, 5)
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Specification
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- Resources
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Current AssigneeKioxia Corporation
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Original AssigneeToshiba Memory Corporation (Kioxia Corporation)
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InventorsShibata, Noboru
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Primary Examiner(s)Dinh, Son T
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Application NumberUS16/023,103Publication NumberTime in Patent Office473 DaysField of Search36518914, 36518915, 36518518US Class CurrentCPC Class CodesG11C 16/10 Programming or data input c...G11C 16/14 Circuits for erasing electr...G11C 16/26 Sensing or reading circuits...G11C 16/3445 Circuits or methods to veri...
