Capacitor structures

• US 10,446,325 B2
• Filed: 09/29/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lu, Wen-Long, Lee, Chi-Chang
• Primary Examiner(s): Ferguson, Dion
• Application Number:
  US15/721,263
• Publication Number:
  US 20190103227A1
• Time in Patent Office: 746 Days
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/1254 based on niobium or tungsteen, tantalum oxides or niobates, tantalates
• CPC Class Codes: H01G 4/224 Housing; Encapsulation
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01G 4/38 Multiple capacitors, i.e. structural combinations of fixed capacitors
• CPC Class Codes: H01G 4/385 Single unit multiple capacitors, e.g. dual capacitor in one coil
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

Claims

1. A capacitor structure, comprising:

a substrate;

a first electrode disposed on the substrate, the first electrode comprising a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer, wherein the substrate defines a cavity and the first conductive post and the second conductive post are disposed within the cavity;

a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post;

a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post; and

a second electrode disposed on the first dielectric layer.

2. The capacitor structure according to claim 1, wherein the planarization layer comprises a polymer layer.

3. The capacitor structure according to claim 2, wherein the polymer layer comprises polyimide.

4. The capacitor structure according to claim 1, wherein the second electrode is disposed in the space between the first conductive post and the second conductive post.

5. The capacitor structure according to claim 1, wherein the space between the first conductive post and the second conductive post constitutes a recess defined by the first conductive post, the second conductive post, and the conductive layer.

6. The capacitor structure according to claim 1, further comprising:

a first conductive contact electrically connected to the first electrode; and

a second conductive contact electrically connected the second electrode.

7. The capacitor structure according to claim 1, wherein the first dielectric layer comprises a metal oxide layer.

8. The capacitor structure according to claim 7, wherein the metal oxide layer comprises tantalum oxide.

9. The capacitor structure according to claim 1, wherein an aspect ratio of at least one of the first conductive post or the second conductive post is equal to or greater than about 7.

10. The capacitor structure according to claim 1, further comprising a second dielectric layer disposed on the second electrode and in the space between the first conductive post and the second conductive post.

11. The capacitor structure according to claim 1, further comprising a third electrode disposed on the second dielectric layer and in the space between the first conductive post and the second conductive post.

12. A capacitor structure, comprising:

a substrate;

a first electrode disposed on the substrate, the first electrode comprising a conductive layer and a plurality of conductive posts;

a first dielectric layer disposed on the first electrode, at least a portion of the first dielectric layer surrounded by the plurality of conductive posts;

a second electrode disposed on the first dielectric layer;

a second dielectric layer disposed on the second electrode;

a third electrode disposed on the second dielectric layer;

a first conductive contact electrically connected to the first and third electrodes; and

a second conductive contact electrically connected to the second electrode.

13. The capacitor structure according to claim 12, further comprising a first conductive via, a second conductive via, and a third conductive via, wherein the first electrode is electrically connected to the first conductive contact by the first conductive via, the second electrode is electrically connected to the second conductive contact by the second conductive via, and the third electrode is electrically connected to the first conductive contact by the third conductive via.

14. The capacitor structure according to claim 12, wherein an aspect ratio of at least one of the plurality of conductive posts is equal to or greater than about 7.

15. The capacitor structure according to claim 12, wherein the substrate defines a cavity accommodating at least one of the plurality of conductive posts.

16. The capacitor structure according to claim 12, further comprising a planarization layer disposed between the first electrode and the first dielectric layer, wherein at least a portion of the planarization layer is surrounded by the plurality of conductive posts.

17. The capacitor structure according to claim 16, wherein at least a portion of the second electrode is surrounded by the first dielectric layer, and wherein at least a portion of the second dielectric layer is surrounded by the second electrode.

18. A method of forming a capacitor structure, comprising:

providing a substrate, wherein the substrate defines a cavity;

forming a first electrode on the substrate, the first electrode comprising a conductive layer and a plurality of conductive posts disposed on and electrically connected to the conductive layer, the plurality of conductive posts defining at least one first recess having one or more sidewalls and a bottom surface, wherein the plurality of conductive posts are disposed within the cavity;

forming a planarization layer overlying the first electrode and covering the one or more sidewalls and the bottom surface of the at least one first recess;

forming a first dielectric layer overlying the planarization layer; and

forming a second electrode overlying the first dielectric layer.

19. The method according to claim 18, wherein forming the planarization layer further comprising:

forming a photosensitive polymer layer on the first electrode and filling at least a portion of the at least one first recess; and

optically removing at least a portion of the photosensitive polymer layer to define at least one second recess.