Polymer frame for a chip, such that the frame comprises at least one via in series with a capacitor

• US 10,446,335 B2
• Filed: 11/27/2014
• Issued: 10/15/2019
• Est. Priority Date: 08/08/2013
• Status: Active Grant

• Current Assignee: Zhuhai Access Semiconductor Company Limited
• Original Assignee: Zhuhai Access Semiconductor Company Limited
• Inventors: Hurwitz, Dror, Huang, Alex
• Primary Examiner(s): Ha, Nguyen T
• Application Number:
  US14/555,633
• Publication Number:
  US 20150228416A1
• Time in Patent Office: 1,783 Days
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01G 17/00 Structural combinations of capacitors or other devices covered by at least two different main groups of this subclass with other electric elements, not covered by this subclass, e.g. RC combinations
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/1209 characterised by the ceramic dielectric material H01G4/1272, H01G4/1281 take precedence
• CPC Class Codes: H01G 4/224 Housing; Encapsulation
• CPC Class Codes: H01G 4/228 Terminals
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/165 : incorporating printed inductors
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09627 : Special connections between adjacent vias, not for grounding vias
• CPC Class Codes: H05K 2201/09672 : Superposed layout, i.e. in different planes
• CPC Class Codes: H05K 2201/098 : Special shape of the cross-section of conductors, e.g. very thick plated conductors
• CPC Class Codes: H05K 2203/308 : Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
• CPC Class Codes: H05K 3/005 : Punching of holes
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs

Abstract

A chip socket defined by an organic matrix framework, wherein the organic matrix framework comprises at least one via post layer where at least one via through the framework around the socket includes at least one capacitor comprising a lower electrode, a dielectric layer and an upper electrode in contact with the via post.

Claims

1. A chip socket for an embedded chip defined by a frame around a socket, the frame having an organic matrix, wherein the frame comprises at least one via post layer comprising at least one via post, wherein at least one capacitor coupled to at least one via post is incorporated within the frame around the chip socket.

2. The chip socket of claim 1, wherein a dielectric of the capacitor comprises at least one of the group consisting of Ta₂O₅, TiO₂, Ba_xSr_1-xTiO₃, BaTiO₃, BaO₄SrTi and Al₂O₃.

3. The chip socket of claim 1, wherein a lower electrode of the capacitor comprises a noble metal.

4. The chip socket of claim 1, wherein the lower electrode of the capacitor comprises a metal selected from the group consisting of gold, platinum and tantalum.

5. The chip socket of claim 1, wherein an upper electrode of the capacitor comprises a metal selected from the group consisting of gold, platinum and tantalum.

6. The chip socket of claim 1, wherein the capacitor comprises a lower electrode layer, a dielectric layer and an upper electrode layer, and the at least one via post stands on the upper electrode layer.

7. The chip socket of claim 1, wherein the capacitor comprises a lower electrode layer and a dielectric layer and the at least one via post stands on the dielectric layer and serves as the upper electrode of the capacitor.

8. The chip socket of claim 7, wherein contact area of the via post in contact with the dielectric layer multipled by dielectric constant of the dielectric layer divided by thickness of the dielectric layer is capacitance of the capacitor.

9. The chip socket of claim 1, wherein the at least one capacitor has a capacitance of between 1.5 pF and 300 pF.

10. The chip socket of claim 1, wherein the at least one capacitor has a capacitance of between 5 pF and 45 pF.

11. The chip socket of claim 1 wherein the frame further comprises at least one feature layer.

12. The chip socket of claim 1, wherein at least one electronic component is embedded within the socket and is electrically coupled to the at least one via.

13. The chip socket of claim 12, wherein the at least one electronic component comprises a second capacitor.

14. The chip socket of claim 13, wherein the second capacitor is a discrete component having a metal termination on at least one end.

15. The chip socket of claim 13, wherein the second capacitor is a Metal-Insulator-Metal (MIM) capacitor.

16. The chip socket of claim 15, wherein the Metal-Insulator-Metal (MIM) capacitor comprises a dielectric layer consisting of at least one of the group consisting of Ta₂O₅, TiO₂, Ba_xSr_1-xTiO₃, BaTiO₃, BaO₄SrTi and Al₂O₃.

17. The chip socket of claim 15, wherein a lower electrode of the Metal-Insulator-Metal (MIM) capacitor comprises a noble metal.

18. The chip socket of claim 15, wherein an upper electrode of the Metal-Insulator-Metal (MIM) capacitor comprises a metal selected from the group consisting of gold, platinum and tantalum.

19. The chip socket of claim 13, wherein the lower electrode comprises a metal selected from the group consisting of gold, platinum and tantalum.

20. The chip socket of claim 13, wherein electrodes of the Metal-Insulator-Metal (MIM) capacitor are coupled to vias by feature layers.

21. The chip socket of claim 20, wherein a feature layer on one side of the frame and embedded components comprises an inductor.

22. The chip socket of claim 20 wherein embedded components within the frame, socket and at least one feature within the feature layer provides a filter.

23. The chip socket of claim 22, wherein the filter is selected from the group consisting of basic LC low pass filters, LC high pass filters, LC series band pass filters, LC parallel band pass filters and Low Pass Parallel-Chebyshev filters.

24. The chip socket of claim 1, wherein a chip mounted in a socket is protected from electromagnetic radiation by a Faraday cage comprising via posts within the frame, thereby minimizing electromagnetic interference.

25. The chip socket of claim 24 wherein at least some of the via posts extend in the XY plane.

26. The chip socket for an embedded chip of claim 1 wherein there are a plurality of chip sockets, each one of the chip sockets defined by a respective frame around a respective socket, the respective frame having an organic matrix, wherein the respective frame comprises at least on via post layer comprising at least one via post, wherein at least one capacitor coupled to at least one via post is incorporated within the respective frame around the chip socket.

27. The chip socket of claim 26 wherein the plurality of chip sockets are arranged as an array.

28. The chip socket of claim 27 wherein at least one processor chip is embedded in a first of the plurality of sockets.

29. The chip socket of claim 28 wherein a passive chip comprising at least one capacitor is embedded in a second of the plurality of sockets.

30. The chip socket of claim 26 wherein the at least one capacitor is coupled with at least one inductor in series.