Semiconductor package with filler particles in a mold compound
First Claim
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1. A semiconductor package, comprising:
- an integrated circuit formed on a semiconductor substrate;
a stress buffer layer on and directly contacting the semiconductor substrate; and
a mold compound on a surface of the stress buffer layer opposite the integrated circuit;
wherein the mold compound comprises a resin, and the resin includes filler particles; and
wherein the filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
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Abstract
A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
15 Citations
19 Claims
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1. A semiconductor package, comprising:
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an integrated circuit formed on a semiconductor substrate; a stress buffer layer on and directly contacting the semiconductor substrate; and a mold compound on a surface of the stress buffer layer opposite the integrated circuit; wherein the mold compound comprises a resin, and the resin includes filler particles; and wherein the filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor package, comprising:
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an integrated circuit formed on a semiconductor substrate; a stress buffer layer on and directly contacting the semiconductor substrate; and a mold compound on a surface of the stress buffer layer opposite the integrated circuit; wherein the mold compound comprises a resin, and the resin includes filler particles; and wherein filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 50 microns. - View Dependent Claims (8, 9, 10)
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11. A semiconductor package, comprising:
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an integrated circuit on a semiconductor substrate, the integrated circuit including at least one capacitor that is sensitive to stress induced by filler particles in a mold compound; a stress buffer layer on and directly contacting a portion of the semiconductor substrate; and the mold compound over a portion of the semiconductor substrate and a portion of the stress buffer layer; wherein the mold compound comprises a resin, and the resin includes filler particles; and wherein filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 50 microns. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method, comprising:
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forming an integrated circuit on a semiconductor substrate; forming a stress buffer layer on and directly contacting the semiconductor substrate; attaching the semiconductor substrate to leads; and applying a mold compound on a surface of the stress buffer layer opposite the integrated circuit, wherein the mold compound comprises a resin, and the resin includes filler particles, and wherein the filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns. - View Dependent Claims (19)
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Specification