Flat metal features for microelectronics applications

• US 10,446,441 B2
• Filed: 05/31/2018
• Issued: 10/15/2019
• Est. Priority Date: 06/05/2017
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Uzoh, Cyprian Emeka
• Primary Examiner(s): Bachner, Robert G
• Assistant Examiner(s): Reida, Molly K
• Application Number:
  US15/994,435
• Publication Number:
  US 20180350674A1
• Time in Patent Office: 502 Days
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 2224/034 by blanket deposition of the material of the bonding area
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03602 Mechanical treatment, e.g. polishing, grinding
• CPC Class Codes: H01L 2224/03848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/039 Methods of manufacturing bonding areas involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/03901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/08121 the connected bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/08123 the bonding area connecting directly to at least two bonding areas
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08147 the bonding area connecting to a bonding area disposed in a recess of the surface of the body
• CPC Class Codes: H01L 2224/80194 Lateral distribution of the bonding areas
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 23/53214 : the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53242 : the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 23/53257 : the principal metal being a refractory metal
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

Abstract

Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

Claims

1. A method, comprising:

creating trenches or cavities for metal features in a substrate suitable for a microelectronic device;

depositing a barrier layer and a first seed layer in the trenches or cavities and on a field of the substrate;

depositing a metal on the first seed layer to partially fill the trenches or cavities with a cavity layer of the metal and to cover the field of the substrate with a field layer of the metal, wherein the field layer has a depth of less than 0.6 microns;

applying resist masking over the field layer;

depositing additional metal in the trenches or cavities to create a cavity layer of the metal thicker than the field layer of the metal;

removing or cleaning the resist masking;

thermally annealing the cavity layer of the metal and the field layer of the metal to create grains of the metal in the cavity layer that are larger than grains of the metal in the field layer;

performing an intermediate chemical-mechanical planarization (CMP) of the cavity layer of the metal and the field layer of the metal;

planarizing the cavity layer of the metal down to the barrier layer covering the field to achieve flat metal features; and

removing the barrier layer covering the field.

2. The method of claim 1, wherein the planarizing creates a metal feature selected from the group consisting of:

a flat metal feature with a width of at least 4 microns (μ

m) and a maximum dishing depth of less than 10 nanometers (nm),

a flat metal feature with a width of at least 10 μ

m and a maximum dishing depth of less than 10 nanometers per micron (nm/μ

m) of depth of the flat metal feature, and

a bonded metallic feature larger than 10 μ

m.

3. The method of claim 1, wherein the depositing the additional metal in the cavities comprises creating a cavity layer of the metal and a field layer of the metal with coplanar top surfaces.

4. The method of claim 1, wherein the depositing the additional metal in the cavities comprises creating a cavity layer of the metal and a field layer of the metal with non-coplanar top surfaces, wherein the surface of the cavity layer is flat and is higher than the surface of the field layer.

5. The method of claim 1, wherein the depositing the additional metal in the cavities comprises creating a cavity layer of the metal and a field layer of the metal with non-coplanar top surfaces, wherein the surface of the cavity layer is non-flat and is mostly higher than the surface of the field layer.

6. The method of claim 2, further comprising:

prior to covering the substrate with the metal to create the cavity layer and the field layer, applying a barrier layer and a first seed layer on the substrate, the first seed layer covering the cavities and the field;

applying a resist masking on a part of the first seed layer covering the field;

applying a second seed layer in the cavities, the second seed layer having a thickness of at least 50 nm;

plating additional metal on the second seed layer in the cavities;

removing the resist masking from the field layer;

depositing additional metal on the cavity layer and on the first seed layer of the field to create a cavity layer of the metal thicker than the field layer of the metal;

thermally annealing the cavity layer of the metal and the field layer of the metal;

performing an intermediate chemical-mechanical planarization (CMP) of the cavity layer of the metal and the field layer of the metal;

planarizing the cavity layer of the metal down to the barrier layer covering the field to achieve the flat metal features; and

removing the barrier layer covering the field.

7. The method of claim 6, wherein the plating additional metal on the second seed layer in the cavities further comprises making a cavity layer of the metal with a top surface higher than the first seed layer on the field;

removing the resist masking on the field; and

performing the step of thermally annealing the cavity layer and the field layer without further plating of metal.

8. The method of claim 2, further comprising:

prior to thermally annealing the metal, depositing a barrier layer and a first seed layer in the cavities and on the field;

depositing the metal on the first seed layer in the cavities and on the field to make a cavity layer filling the cavities, the cavity layer approximately the same thickness as the field layer, and the field layer having a greater thickness than an overburden part of the cavity layer over the cavities;

selectively masking the cavity layer of the metal over the cavities;

etching the field layer of the metal to less than 0.6 microns in thickness, wherein a thickness of the cavity layer is greater than a thickness of the field layer of the metal; and

performing the step of thermally annealing the metal to create large grains of the metal in the cavity layer of the metal and small grains of the metal in the field layer of the metal.

9. The method of claim 2, further comprising:

prior to thermally annealing the metal, depositing a barrier layer and a first seed layer in the cavities and on the field;

depositing the metal on the first seed layer in the cavities and on the field to make a cavity layer filling the cavities, the cavity layer approximately the same thickness as the field layer, and the field layer having a greater thickness than an overburden part of the cavity layer over the cavities;

planarizing the cavity layer and the field layer to a coplanar surface, wherein the field layer has a thickness approximately equal to an overburden part of the cavity layer over the cavities; and

performing the step of thermally annealing the metal to create large grains of the metal in the cavity layer of the metal and small grains of the metal in the field layer of the metal.

10. The method of claim 9, further comprising, prior to the planarizing the cavity layer and the field layer to a coplanar surface, storing the metal-covered substrate at a low temperature to suppress metal grain growth;

planarizing the cavity layer and the field layer of the cooled metal-covered substrate at the low temperature to a coplanar surface, wherein the field layer has a thickness approximately equal to an overburden part of the cavity layer over the cavities; and

performing the step of thermally annealing the metal to create large grains of the metal in the cavity layer of the metal and small grains of the metal in the field layer of the metal.

11. A method, comprising:

creating trenches or cavities for metal features in a substrate suitable for a microelectronic device;

applying a barrier layer and a first seed layer on the substrate, the first seed layer covering the trenches or cavities and the field;

applying a resist masking on a part of the first seed layer covering the field;

applying a second seed layer in the trenches or cavities, the second seed layer having a thickness of at least 50 nm;

plating additional metal on the second seed layer in the trenches or cavities;

removing the resist masking from the field layer;

depositing additional metal on the cavity layer and on the first seed layer of the field to create a cavity layer of the metal thicker than the field layer of the metal;

thermally annealing the metal to create grains of the metal in the cavity layer of the metal that are larger than grains of the metal in the field layer of the metal;

performing an intermediate chemical-mechanical planarization (CMP) of the cavity layer of the metal and the field layer of the metal;

planarizing the cavity layer of the metal down to the barrier layer covering the field to achieve a flat metal feature selected from the group consisting of;

a flat metal feature with a width of at least 4 microns (μ

m) and a maximum dishing depth of less than 10 nanometers (nm),

a flat metal feature with a width of at least 10 μ

m and a maximum dishing depth of less than 10 nanometers per micron (nm/μ

m) of depth of the flat metal feature, and

a bonded metallic feature larger than 10 μ

m; and

removing the barrier layer covering the field.

12. The method of claim 11, wherein the plating additional metal on the second seed layer in the trenches or cavities further comprises making a cavity layer of the metal with a top surface higher than the first seed layer on the field;

removing the resist masking on the field; and

performing the step of thermally annealing the cavity layer and the field layer without further plating of metal.

13. A method, comprising:

creating trenches or cavities for metal features in a substrate suitable for a microelectronic device;

depositing a barrier layer and a first seed layer in the trenches or cavities and on the field;

depositing a metal on the first seed layer in the trenches or cavities and on the field to make a cavity layer filling the trenches or cavities, the cavity layer approximately the same thickness as the field layer, and the field layer having a greater thickness than an overburden part of the cavity layer over the trenches or cavities;

selectively masking the cavity layer of the metal over the trenches or cavities;

etching the field layer of the metal to less than 0.6 microns in thickness, wherein a thickness of the cavity layer is greater than a thickness of the field layer of the metal;

thermally annealing the metal to create grains of the metal in the cavity layer of the metal that are larger than grains of the metal in the field layer of the metal; and

planarizing at least the grains of the metal in the cavity layer of the metal to achieve a flat conductive metal feature of the microelectronic device selected from the group consisting of;

a flat metal feature with a width of at least 4 microns (μ

m) and a maximum dishing depth of less than 10 nanometers (nm),

a flat metal feature with a width of at least 10 μ

m and a maximum dishing depth of less than 10 nanometers per micron (nm/μ

m) of depth of the flat metal feature, and

a bonded metallic feature larger than 10 μ

m.

14. A method, comprising:

creating trenches or cavities for metal features in a substrate suitable for a microelectronic device;

depositing a barrier layer and a first seed layer in the trenches or cavities and on the field;

depositing the metal on the first seed layer in the trenches or cavities and on the field to make a cavity layer filling the trenches or cavities, the cavity layer approximately the same thickness as the field layer, and the field layer having a greater thickness than an overburden part of the cavity layer over the trenches or cavities;

storing the metal-covered substrate at a low temperature to suppress metal grain growth;

planarizing the cavity layer and the field layer of the cooled metal-covered substrate at the low temperature to a coplanar surface, wherein the field layer has a thickness approximately equal to an overburden part of the cavity layer over the trenches or cavities;

thermally annealing the metal to create grains of the metal in the cavity layer of the metal that are larger than grains of the metal in the field layer of the metal;

planarizing the cavity layer and the field layer down to the barrier layer of the field to achieve a flat conductive metal feature of the microelectronic device selected from the group consisting of;

a flat metal feature with a width of at least 4 microns (μ

m) and a maximum dishing depth of less than 10 nanometers (nm),

a flat metal feature with a width of at least 10 μ

m and a maximum dishing depth of less than 10 nanometers per micron (nm/μ

m) of depth of the flat metal feature, and

a bonded metallic feature larger than 10 μ

m.