Method and structure for enabling controlled spacer RIE

• US 10,446,452 B2
• Filed: 04/17/2017
• Issued: 10/15/2019
• Est. Priority Date: 06/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Jung, Ryan O., Lie, Fee Li, Miller, Eric R., Shearer, Jeffrey C., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Campbell, Shaun M
• Assistant Examiner(s): Chi, Suberr L
• Application Number:
  US15/489,303
• Publication Number:
  US 20170221773A1
• Time in Patent Office: 911 Days
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

Claims

1. A semiconductor structure comprising:

a plurality of semiconductor fins extending upwards from a first portion of a substrate;

a plurality of sacrificial spacer fin portions extending upwards from a second portion of said substrate;

a gate structure straddling over each semiconductor fin and each sacrificial spacer fin portion;

a gate spacer surrounding said gate structure, wherein an entirety of each sacrificial spacer fin portion is located beneath a portion of said gate structure and a portion of said gate spacer, wherein said gate structure is a functional gate structure comprising a U-shaped gate dielectric portion that has a topmost surface that is coplanar with a topmost surface of said gate spacer.

2. The semiconductor structure of claim 1, wherein said substrate is an insulator layer.

3. The semiconductor structure of claim 1, wherein said gate spacer and each sacrificial spacer fin portion comprise a same dielectric material.

4. The semiconductor structure of claim 3, wherein said same dielectric material is silicon nitride.

5. The semiconductor structure of claim 1, wherein said semiconductor fins are present in a FinFET device region, while each sacrificial spacer fin portion is present in a kerf region.

6. The semiconductor structure of claim 1, wherein each of the plurality of semiconductor fins has a height and width that is the same as each sacrificial spacer fin portion.

7. The semiconductor structure of claim 6, wherein each sacrificial spacer fin portion has a same pitch as a pitch of each semiconductor fin.

8. The semiconductor structure of claim 1, wherein a first portion of each semiconductor fin is located beneath said gate structure and a portion of said gate spacer, and a second portion of each semiconductor fin, which is contiguous with the first portion, extends beyond the outermost edge of the gate spacer.

9. The semiconductor structure of claim 8, further comprising a source/drain region located on the second portion of each semiconductor fin and on both sides of said gate structure.

10. The semiconductor structure of claim 1, further comprising an interlevel dielectric material contacting physically exposed sidewalls of said gate spacer and having a bottommost surface located directly on a physically exposed surface of said substrate.

11. The semiconductor structure of claim 10, wherein said interlevel dielectric material has a topmost surface that is coplanar with a topmost surface of said gate spacer.

12. The semiconductor structure of claim 1, wherein said semiconductor fins and said sacrificial spacer fin portions are spaced apart from each other, and are oriented parallel to each other.

13. The semiconductor structure of claim 1, wherein each semiconductor fin has a bottommost surface that is located on said substrate, and is coplanar with a bottommost surface of each sacrificial spacer fin portion.

14. A semiconductor structure comprising:

a plurality of semiconductor fins extending upwards from a first portion of a substrate;

a plurality of sacrificial spacer fin portions extending upwards from a second portion of said substrate;

a gate structure straddling over each semiconductor fin and each sacrificial spacer fin portion; and

a gate spacer surrounding said gate structure, wherein an entirety of each sacrificial spacer fin portion is located beneath a portion of said gate structure and a portion of said gate spacer, wherein said gate structure is a sacrificial gate structure, and wherein a portion of a protective dielectric liner is positioned between a bottommost surface of said sacrificial gate structure and a topmost surface of said semiconductor fins, and said portion of said protective dielectric liner has sidewall surfaces that are vertically coincident to sidewall surfaces of said sacrificial gate structure.