Stacked semiconductor dies including inductors and associated methods

• US 10,446,527 B2
• Filed: 09/11/2018
• Issued: 10/15/2019
• Est. Priority Date: 08/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nakano, Eiichi
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US16/128,414
• Publication Number:
  US 20190067253A1
• Time in Patent Office: 399 Days
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06515 Bonding areas having different functions
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.

Claims

1. A semiconductor device comprising:

a package substrate having an upper surface and a lower surface, wherein the upper surface is continuous;

a stack of dies attached to the upper surface of the substrate, wherein the stack includes—

a first die including a front side and one or more first inductors at the front side; and

a second die disposed over and offset from the first die, the second die including a front side facing the first die and one or more second inductors at the front side of the second die, wherein one or more of the second inductors are inductively coupled to one or more first inductors;

a first plurality of wirebonds electrically coupling a first plurality of substrate bond pads on the upper surface of the substrate to a first plurality of die bond pads on the front side of the first die, wherein the upper surface of the substrate remains continuous between the first plurality of substrate bond pads and the stack of dies after the semiconductor device is manufactured; and

a second plurality of wirebonds electrically coupling a second plurality of substrate bond pads on the lower surface of the substrate to a second plurality of die bond pads on the front side of the second die.

2. The device of claim 1 wherein the second plurality of die bond pads is located in a peripheral portion of the second die that overhangs the first die.

3. The device of claim 1, further comprising a first die attach film between the substrate and the first die and a second die attach film between the first die and the second die.

4. The device of claim 1 wherein the first inductors include at least one active inductor and at least one orphaned inductor, wherein the active inductor is aligned with a corresponding second inductor and the orphaned inductor is not aligned with a second inductor.

5. The device of claim 1 wherein the first and second dies are homogeneous.

6. The device of claim 1 wherein the first and second dies are configured to wirelessly communicate via the first and second inductors.

7. The device of claim 1 wherein one or more of the first and second inductors each include a transceiver coil and a receiver coil, wherein the receiver coil is separated from the transceiver coil and generally co-planar with the transceiver coil.

8. The device of claim 1 wherein the first die includes silicon, and wherein the first inductors are embedded in the first die such that each first inductive link is separated from an active surface of the first die by a portion of the silicon.

9. The device of claim 1 further comprising a plurality of electrical connectors on the lower surface of the substrate and configured to electrically couple the substrate to an external package site.

10. The device of claim 1 wherein the stack further comprises:

a third die disposed over the second die, the third die including a front side and one or more third inductors at the front side of the third die; and

a fourth die disposed over and offset from the third die, the fourth die including a front side facing the third die and one or more fourth inductors at the front side of the fourth die, wherein one or more of the fourth inductors are inductively coupled to the one or more of the third inductors.

11. The device of claim 10 further comprising:

a third plurality of wirebonds electrically coupling the fourth die to the second die; and

a fourth plurality of wirebonds electrically coupling the second plurality of die bond pads on the front side of the second die to a third plurality of die bond pads on the front side of the fourth die.

12. The device of claim 10 wherein—

the second die is offset from the first die in a first direction,

the fourth die is offset from the third die in the first direction, and

the third die is aligned with the second die along an axis normal to the upper surface of the substrate.

13. A semiconductor device, comprising:

a substrate having an upper surface and a lower surface;

a first die mounted to the substrate and including a first active side and first inductors at the first active side;

a second die mounted to the first die in an offset position such that a portion of the second die extends beyond the first die, wherein the second die includes a second active side facing the first die and second inductors at the second active side of the second die, and wherein one or more of the first inductors is inductively coupled to one or more corresponding second inductors;

first interconnects electrically coupling the substrate to the first die; and

second interconnects electrically coupling and extending from the second active side of the second die to the lower surface of substrate; and

a mold material encapsulating only a portion of the second interconnects.

14. The device of claim 13 wherein the second interconnects electrically couple first substrate bond pads at the lower surface of the substrate to first die bond pads at the portion of the second die extending beyond the first die.

15. The device of claim 13 wherein the first die and the second die are homogeneous.

16. The device of claim 13 wherein the first die includes silicon, and wherein the first inductors are embedded in the first die such that each of the first inductors is separated from a first surface of the first die by a portion of the silicon.

17. The device of claim 13 wherein the substrate is a first substrate, and wherein the first substrate, the first die, the second die, the first plurality of interconnects, and the second plurality of interconnects together comprise a first stacked package, the device further comprising a second stacked package spaced apart from the first stacked package and including:

a second substrate having an upper surface and a lower surface;

a third die mounted to the upper surface of the second substrate and including an active side and a plurality of third inductors at the active side of the third die;

a fourth die mounted to the third die in an offset position such that an edge of the fourth die extends beyond a corresponding edge of the third die, wherein the fourth die includes an active side and a plurality of fourth inductors at the active side of the fourth die, and wherein one or more of the third inductors are inductively coupled to one or more corresponding fourth inductors; and

a third plurality of interconnects electrically coupling the second substrate to the third die; and

a fourth plurality of interconnects electrically coupling and extending from the active side of the fourth die to the lower surface of second substrate.

18. The device of claim 17, further comprising a mold material at least partially encapsulating the first and second stacked configurations.