Package on package with integrated passive electronics method and apparatus

• US 10,446,533 B2
• Filed: 09/29/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kim, Hyoung Il
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US15/721,057
• Publication Number:
  US 20190103388A1
• Time in Patent Office: 746 Days
• Field of Search: 438106, 438107, 438108, 438110, 438127
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/1815 Shape

Abstract

The present application relates to devices and techniques for a package on package multi-package integrated circuit. A component of the integrated circuit maybe located in a void formed in a circuit package of the multi-package integrated circuit. The void may be formed by fabricating a void structure with an internal void corresponding to the component. The void structure may be bonded to a first substrate of a first package in the multi-package integrated circuit. The first substrate and void structure may be encased in a mold compound. A sacrificial layer may be removed, exposing the void in the void structure. The component may be, for example, a through mold via. The first package may be coupled to a second package. Multi-package integrated circuit assemblies fabricated pursuant to the disclosure herein may comprise a higher density of electronic components, including passive electronic components.

Claims

1. A method of fabricating a multi-package integrated circuit comprising:

forming a bottom circuit package, including providing a bottom circuit package substrate, placing a first integrated circuit on the substrate;

disposing a mold compound layer on the substrate to encapsulate the first integrated circuit; and

disposing first and second void structures in the mold compound layer, wherein the first and second void structures have first and second heights, wherein the first height is greater than the second height, wherein forming the bottom circuit package further includes disposing a conductor via through the mold compound layer, including forming the conductor via with vertical sidewalls in the mold compound, and filling the conductor via with a conductive material;

forming a top circuit package, including providing a top circuit package substrate;

disposing a second integrated circuit in a die side layer of the top circuit package substrate; and

disposing first and second passive electrical components on an interface side of the top package substrate to match the disposition of the first and second void structures of the bottom package substrate, wherein the first and second passive electrical components have first and second component heights that respectively match the first and second heights of the first and second void structures, wherein the first component height is greater than the second component height; and

mounting the top circuit package to the bottom circuit package, including inserting the first and second passive electrical components in the first and second void structures respectively; and

electrically coupling the bottom circuit package to the interface side of the top circuit package substrate, wherein the conductor via with vertical sidewalls provides at least a part of the electrical coupling between the top and bottom circuit packages.

2. The method according to claim 1, further comprising electrically coupling the first and second passive electrical components to the interface side of the top circuit package substrate before mounting the top circuit package substrate to the bottom circuit package.

3. The method according to claim 1, wherein the first and second passive electrical components comprise at least one of a resistor, capacitor, power component, or through mold via (TMV).

4. The method according to claim 3, wherein mounting the top circuit package substrate to the bottom circuit package is performed by reflow soldering.

5. The method according to claim 1, further comprising forming a vertical wall of the first and second void structures to be disposed perpendicular to a horizontal floor of the first and second void structures.

6. The method according to claim 1, further comprising removing a sacrificial layer from the bottom circuit package to expose the first and second void structures.

7. The method according to claim 1, wherein disposing the first and second void structures includes at least one of mechanical drilling, laser drilling, or chemical etching of the mold compound layer.

8. The method according to claim 1, wherein mounting the top circuit package to the bottom circuit package includes electrically coupling the top circuit package and the bottom circuit package with a first ball grid array, wherein the bottom circuit package comprises an interface side of a bottom circuit package substrate, and electrically coupling the interface side of the bottom circuit package substrate to a motherboard with a second ball grid array.

9. The method according to claim 8, wherein the second ball grid array forms more electrical contacts between the interface side of the bottom circuit package substrate and the motherboard than the first ball grid array forms electrical contacts between the interface side of the top circuit package substrate and the bottom circuit package.