Routing for three-dimensional integrated structures

• US 10,446,535 B2
• Filed: 04/25/2016
• Issued: 10/15/2019
• Est. Priority Date: 12/18/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Ayres, Alexandre, Borot, Bertrand
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US15/137,201
• Publication Number:
  US 20170179104A1
• Time in Patent Office: 1,268 Days
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

Claims

1. A three-dimensional integrated structure, comprising:

a first substrate having a peripheral edge in a shape which includes four sides and four right angles, the first substrate including a plurality of first transistors having gate lines which extend parallel to each other and are oriented in a first direction that is parallel to a side of the shape of the first substrate,

a first interconnection level over the first substrate and which includes first electrically conducting tracks extending in directions parallel to the four sides of the shape of the first substrate,

a second substrate having a peripheral edge in a shape which includes four sides and four right angles, the second substrate including a plurality of second transistors having gate lines which extend parallel to each other and are oriented in a second direction which makes a non-right and non-zero angle with a side of the shape of the second substrate,

a second interconnection level over the second substrate and which includes second electrically conducting tracks extending directions parallel to and orthogonal to the second direction, and

wherein the first and second interconnection levels face each other and electric connections are present between ones of the first and second electrically conducting tracks.

2. The structure according to claim 1, wherein the non-right and non-zero angle is an angle of 45°

.

3. The structure according to claim 1, wherein each of the first and second interconnection levels includes a plurality of metallization levels, each metallization level containing electrically conducting tracks.

4. The structure according to claim 1, wherein the four sides of the shape of the first substrate extend parallel corresponding ones of the four sides of the shape of the second substrate.

5. The structure according to claim 1, wherein the four sides of the shape of the first substrate are aligned with corresponding ones of the four sides of the shape of the second substrate.

6. The structure according to claim 1, wherein the electric connections between ones of the first and second electrically conducting tracks comprise electrically conducting pillars.

7. The structure according to claim 1, wherein the electric connections between ones of the first and second electrically conducting tracks comprise hybrid bondings.

8. A three-dimensional integrated structure, comprising:

a first substrate having a peripheral edge in a shape which includes four sides and four right angles, the first substrate including a plurality of first transistors having gate lines which extend parallel to each other and are oriented in a first direction that is parallel to a side of the shape of the first substrate,

a first interconnection level over the first substrate and which includes first electrically conducting tracks extending in directions parallel to the four sides of the shape of the first substrate,

a second substrate having a peripheral edge in a shape which includes four sides and four right angles, the second substrate including a plurality of second transistors having gate lines which extend parallel to each other and are oriented in a second direction which makes a non-right and non-zero angle with a side of the shape of the second substrate,

a second interconnection level over the second substrate and which includes second electrically conducting tracks extending directions parallel to and orthogonal to the second direction, and

wherein the first interconnection level faces a bottom surface of the second substrate and electric connections are present between ones of the first and second electrically conducting tracks.

9. The structure according to claim 8, wherein the non-right and non-zero angle is an angle of 45°

.

10. The structure according to claim 8, wherein each of the first and second interconnection levels includes a plurality of metallization levels, each metallization level containing electrically conducting tracks.

11. The structure according to claim 8, wherein the four sides of the shape of the first substrate extend parallel corresponding ones of the four sides of the shape of the second substrate.

12. The structure according to claim 8, wherein the four sides of the shape of the first substrate are aligned with corresponding ones of the four sides of the shape of the second substrate.

13. The structure according to claim 8, wherein the electric connections between ones of the first and second electrically conducting tracks comprise through silicon vias which extend through the second substrate.

14. A three-dimensional integrated structure, comprising:

a first substrate having a peripheral edge in a shape which includes four sides and four right angles, the first substrate including a plurality of first transistors having gate lines which extend parallel to each other and are oriented in a first direction that is parallel to a side of the shape of the first substrate,

an interconnection level over the first substrate and which includes electrically conducting tracks extending in directions parallel to the four sides of the shape of the first substrate,

a second substrate having a peripheral edge in a shape which includes four sides and four right angles, the second substrate including a plurality of second transistors having gate lines which extend parallel to each other and are oriented in a second direction which makes a non-right and non-zero angle with a side of the shape of the second substrate, and

wherein the second substrate faces a bottom surface of the first substrate and electric connections are present between the second transistors and the electrically conducting tracks.

15. The structure according to claim 14, wherein the non-right and non-zero angle is an angle of 45°

.

16. The structure according to claim 14, wherein the interconnection level includes a plurality of metallization levels, each metallization level containing electrically conducting tracks.

17. The structure according to claim 14, wherein the four sides of the shape of the first substrate extend parallel corresponding ones of the four sides of the shape of the second substrate.

18. The structure according to claim 14, wherein the four sides of the shape of the first substrate are aligned with corresponding ones of the four sides of the shape of the second substrate.

19. The structure according to claim 14, wherein the electric connections between the second transistors and the electrically conducting tracks comprise through silicon vias which extend through the first substrate.