Electrostatic discharge protection structure and fabrication method thereof

• US 10,446,538 B2
• Filed: 09/20/2018
• Issued: 10/15/2019
• Est. Priority Date: 01/06/2016
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Zhou, Fei
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Isaac, Stanetta D
• Application Number:
  US16/136,671
• Publication Number:
  US 20190019788A1
• Time in Patent Office: 390 Days
• Field of Search: None
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0296 involving a specific disposition of the protective devices
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.

Claims

1. A method for fabricating an ESD protection structure, comprising:

forming a substrate having a first region and a second region, wherein the first region and the second region are separated by a preset distance;

forming a well area in the substrate, wherein the well area covers the first region, the second region, and a region between the first region and the second region;

forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region, wherein the first fin portion has first-type doping ions and the second fin portion has second-type doping ions;

forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and covering portions of top and side surfaces of the first fin portion, and a second supporting gate crossing the second fin portion and covering portions of top and side surfaces of the second fin portion;

forming a dielectric layer on the well area between the first region and the second region, and between the first fin portion, the second fin portion, and the supporting gate structure, wherein the supporting gate structure is in the dielectric layer;

forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and being configured to connect to a first bias voltage, and a second conductive structure connecting to the second fin portion and being configured to connect to a second bias voltage, and the first bias voltage and the second bias voltage are not equal to one another; and

forming a first conductive layer on the dielectric layer and a top surface of the first supporting gate, and a second conductive layer on the dielectric layer and a top surface of the second supporting gate.

2. The method according to claim 1, wherein:

the first supporting gate is electronically connected to the first bias voltage; and

the second supporting gate is electronically connected to the second bias voltage.

3. The method according to claim 1,

wherein the first conductive layer is contacted with the first supporting gate and the first conductive structure, receiving the first bias voltage;

and

the second conductive layer is contacted with the second supporting gate and the second conductive structure, receiving the second bias voltage.

4. The method according to claim 3, wherein forming the dielectric layer includes:

forming a dielectric material layer covering the well area between the first region and the second region, the first fin portion, the second fin portion, and the supporting gate structure; and

planarizing the dielectric material layer by a chemical mechanical polishing process to form the dielectric layer, such that the dielectric layer exposes the supporting gate structure.

5. The method according to claim 1, after forming the supporting gate structure and before forming the dielectric layer, further including:

forming a first epitaxial layer in the first fin portion at both sides of the first supporting gate, wherein the first epitaxial layer has the first-type doping ions; and

forming a second epitaxial layer in the second fin portion at both sides of the second supporting gate, wherein the second epitaxial layer has the second-type doping ions;

wherein the first conductive structure connects to the first fin portion through the first epitaxial layer; and

the second conductive structure connects to the second fin portion through the second epitaxial layer.

6. The method according to claim 1, wherein:

the supporting gate structure is a dummy gate;

the supporting gate structure is made of polysilicon;

or

the supporting gate structure is a polysilicon gate or a metal gate.

7. The method according to claim 1, wherein:

the first conductive structure crosses the first fin portion, and the first conductive structure covers portions of top and side surfaces of the first fin portion; and

the second conductive structure crosses the second fin portion, and the second conductive structure covers portions of top and side surfaces of the second fin portion.

8. The method according to claim 1, wherein:

the first conductive structure and the first supporting gate are arranged in parallel; and

the second conductive structure and the second supporting gate are arranged in parallel.

9. The method according to claim 1, wherein:

a number of the first conductive structure and the second conductive structure is more than one;

a number of the first supporting gate and the second supporting gate is more than one;

the first conductive structure and the first supporting gate are alternately arranged; and

the second conductive structure and the second supporting gate are alternately arranged.

10. The method according to claim 1, wherein:

the first conductive layer and the second conductive layer are bar-shaped;

the first supporting gate and the first conductive structure are arranged in parallel, and the first conductive layer is vertically arranged with the first supporting gate and the first conductive structure; and

the second supporting gate and the second conductive structure are arranged in parallel, and the second conductive layer is vertically arranged with the second supporting gate and the second conductive structure.

11. The method according to claim 1, wherein:

the second region surrounds the first region.

12. The method according to claim 1, wherein:

the first region is a square-shaped region; and

the second region is a square annular-shaped region.

13. The method according to claim 1, wherein:

the preset distance between the first region and the second region is in a range of approximately 0.2-1 μ

m.

14. The method according to claim 1, wherein:

a first epitaxial layer is formed in the first fin portion at both sides of the first supporting gate, wherein the first epitaxial layer has the first-type doping ions;

a second epitaxial layer is formed in the second fin portion at both sides of the second supporting gate, wherein the second epitaxial layer has the second-type doping ions;

the first conductive structure connects to the first fin portion through the first epitaxial layer; and

the second conductive structure connects to the second fin portion through the second epitaxial layer.

15. The method according to claim 14, wherein:

the first epitaxial layer is an “

Σ

”

shaped epitaxial layer made of silicon and germanium materials; and

the second epitaxial layer is a square-shaped epitaxial layer made of silicon and carbon materials.

16. The method according to claim 1, wherein:

the first-type doping ions are P-type ions;

the second-type doping ions are N-type ions; and

the well area is an N-type well area.

17. The method according to claim 1, wherein:

the first region is configured to form a first anode connected to a ground;

the second region is configured to form a second anode connected to the ground.

18. The method according to claim 1, wherein:

the first supporting gate divides the first epitaxial layer into many small-area epitaxial layers; and

the second supporting gate divides the second epitaxial layer into many small-area epitaxial layers.

19. The method according to claim 1, wherein:

the second region is in parallel with the first region.

20. The method according to claim 1, wherein:

a top surface of the supporting gate structure is coplanar with a top surface of the dielectric layer and a top surface of the conductive structure.