Bidirectional switch having back to back field effect transistors

• US 10,446,545 B2
• Filed: 06/30/2016
• Issued: 10/15/2019
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Lui, Sik
• Primary Examiner(s): Gondarenko, Natalia A
• Application Number:
  US15/199,828
• Publication Number:
  US 20180006026A1
• Time in Patent Office: 1,202 Days
• Field of Search: 257330, 257331, 257334, 257328, 257262, 257E29262, 257E2141, 257566, 257 48, 257139, 257365, 257E27062, 257E21629, 257E27055, 257E2706, 438524, 438270
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7404 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.

Claims

1. A bi-directional semiconductor switching device, comprising:

first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate, wherein a source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side, wherein gates for both the first and second FETs are disposed in tandem in a common set of trenches formed in an epitaxial layer of the semiconductor substrate, wherein the source for the second FET is between a bottom of the common set of trenches and a bottom of the semiconductor substrate, wherein the epitaxial layer includes a drift region sandwiched between the source for the first FET and the source for the second FET and forms a common drain for both the first FET and second FET, wherein the source for the first FET is formed in the upper portion of the epitaxial layer and the semiconductor substrate includes a substrate layer of a first conductivity type that acts as the source for the second FET, wherein the drift region is of a same conductivity type as the source for the first FET and the source for the second FET but at a lower carrier concentration than that of the source for the first FET and the source for the second FET.

2. The device of claim 1, wherein the drift region is formed between the substrate layer and a first body region of the first FET that is of a second conductivity type opposite the first conductivity type, and one or more second body regions of the second conductivity type formed for the second FET formed such that the drift region is sandwiched between the first body region and the one or more second body regions;

wherein the common set of trenches includes a plurality of trenches formed in the semiconductor substrate from the first side through the first body region, the drift region and into the one or more second body regions.

3. The device of claim 2, wherein the one or more body regions of the second FET include a first epitaxial layer of the second conductivity type that is opposite the first conductivity type, and wherein the drift region includes a second epitaxial layer of the first conductivity type formed on the first epitaxial layer whereby the first epitaxial layer is sandwiched between the substrate layer and the second epitaxial layer.

4. The device of claim 3, wherein the first and second FETs are both metal oxide semiconductor FETs (MOSFETs), wherein a heavily doped region of the first conductivity type disposed in the first epitaxial layer extends at least from a bottom of each of the common set of trenches down to the substrate layer of the first conductivity type.

5. The device of claim 4, wherein the first epitaxial layer of the second conductivity type is electrically connected to a metal layer disposed on the first side of the semiconductor substrate through a conductive plug disposed in a bottom body contact trench.

6. The device of claim 5, wherein the conductive plug disposed in the bottom body contact trench extends through the first epitaxial layer of the second conductivity type into the substrate layer of the first conductivity type.

7. The device of claim 1, wherein the first FET is a metal oxide semiconductor FET (MOSFET) and the second FET is an accumulation mode FET (ACCUFET) with a diode connected in parallel to the ACCUFET.

8. The device of claim 7, wherein a doped region of a second conductivity type opposite the first conductivity type is disposed in the epitaxial layer under a bottom of each trench of the common set of trenches separated away from the substrate layer of the first conductivity type.

9. The device of claim 8, wherein the doped region of the second conductivity type being electrically connected to the substrate layer of the first conductivity type.

10. The device of claim 9, wherein the doped region of the second conductivity type being electrically connected to a metal layer disposed on the first side of the semiconductor substrate through a conductive plug disposed in a contact trench.

11. The device of claim 10, wherein the conductive plug disposed in the contact trench extend through the doped region of the second conductivity type and the epitaxial layer into the substrate layer of the first conductivity type.

12. The device of claim 1 further comprising a first metal layer formed on the first side of the substrate, wherein the source for the first FET is electrically connected to a first portion of the first metal layer, wherein the source for the second FET is electrically connected to a second portion of the first metal layer.