Cut inside replacement metal gate trench to mitigate N-P proximity effect

• US 10,446,550 B2
• Filed: 10/13/2017
• Issued: 10/15/2019
• Est. Priority Date: 10/13/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kannan, Balaji, Ozbek, Ayse M., Chu, Tao, Haran, Bala, Chhabra, Vishal, Onishi, Katsunori, Xu, Guowei
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/783,549
• Publication Number:
  US 20190115346A1
• Time in Patent Office: 732 Days
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

Claims

1. A structure, comprising:

a first device;

a second device, adjacent to the first device;

a dielectric material, of the first device and the second device;

a cut in the dielectric material within a trench between the first device and the second device; and

a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut,

wherein the first device is an NFET and the second device is a PFET.

2. The structure of claim 1, wherein the dielectric material is high-k dielectric material.

3. The structure of claim 1, wherein the cut removes an oxygen transport conduit from the PFET to the NFET.

4. The structure of claim 1, wherein the common gate electrode is deposited on a workfunction metal of the PFET.

5. The structure of claim 4, wherein the underlying material within the cut is insulator material.

6. The structure of claim 1, wherein the cut separates the dielectric material in the trench, with the dielectric material remaining on the first device and the second device.

7. The structure of claim 6, wherein the dielectric material is not shared between the first device and the second device.

8. The structure of claim 6, wherein the dielectric material is a discontinuous gate dielectric material for a NFET device and a PFET device.

9. The structure of claim 6, wherein the discontinuous gate dielectric material is a separate gate dielectric material for the NFET device and the PFET device such that the NFET device and the PFET device do not share a common gate dielectric material.

10. A structure, comprising:

an NFET device;

a PFET device, adjacent to the NFET device;

a discontinuous gate dielectric material for the NFET device and the PFET device; and

a common gate electrode shared with the PFET device and the NFET device,

wherein the discontinuous gate dielectric material includes a cut which separates the gate dielectric material over the NFET device and the PFET device and the common gate electrode contacts insulator material within the cut.

11. The structure of claim 10, wherein the discontinuous gate dielectric material includes the cut in a gate trench between the NFET device and the PFET device.

12. The structure of claim 11, wherein the common gate electrode is within the cut, directly contacting the insulation material.

13. The structure of claim 12, wherein the cut removes an oxygen transport conduit from the PFET device to the NFET device.

14. The structure of claim 12, wherein the cut preserves a Vt of the NFET device.

15. The structure of claim 12, wherein the common gate electrode is deposited on a workfunction metal of the PFET device.

16. The structure of claim 15, further comprising a common metal deposited on the common gate electrode.

17. The structure of claim 10, wherein the discontinuous gate dielectric material is not shared between the NFET device and the PFET device.