Semiconductor device

• US 10,446,551 B2
• Filed: 03/23/2017
• Issued: 10/15/2019
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Aoki, Takeshi
• Primary Examiner(s): Alam, Mohammed R
• Application Number:
  US15/467,142
• Publication Number:
  US 20170194327A1
• Time in Patent Office: 936 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a first electrode, a second electrode, and a third electrode over the semiconductor layer, wherein the second electrode is between the first electrode and the third electrode;

a first insulating film over the first electrode, the second electrode, and the third electrode;

a first wiring overlapping the first electrode with the first insulating film therebetween;

a second wiring overlapping the semiconductor layer with the first insulating film therebetween, in a first region between the first electrode and the second electrode;

a third wiring overlapping the semiconductor layer with the first insulating film therebetween, in a second region between the second electrode and the third electrode;

a fourth wiring overlapping the third electrode with the first insulating film therebetween;

a second insulating film over the first wiring, the second wiring, the third wiring, and the fourth wiring; and

a fifth wiring over the second insulating film and electrically connected to the second electrode through a contact hole in the second insulating film,

wherein the first wiring, the second wiring, the third wiring, and the fourth wiring are parallel to one another, and

wherein the fifth wiring is perpendicular to the first wiring.

2. The semiconductor device according to claim 1, wherein the first electrode faces a top surface of the semiconductor layer and a side surface of the semiconductor layer.

3. The semiconductor device according to claim 1, wherein the first wiring faces a top surface of the semiconductor layer and a side surface of the semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the second wiring is electrically connected to a word line driver circuit, and

wherein the fifth wiring is electrically connected to a bit line driver circuit.

5. The semiconductor device according to claim 1, wherein the contact hole is located between the second wiring and the third wiring.

6. The semiconductor device according to claim 1, wherein each of the first electrode, the second electrode, and the third electrode is in contact with the semiconductor layer.

7. The semiconductor device according to claim 1, further comprising an interlayer insulating film over the second insulating film, wherein the fifth wiring is located over the interlayer insulating film.

8. The semiconductor device according to claim 1, wherein the second wiring partly overlaps the first electrode and the second electrode.

9. The semiconductor device according to claim 1, wherein the semiconductor layer comprises indium and zinc.

10. The semiconductor device according to claim 1,

wherein the first wiring overlaps the semiconductor layer, and

wherein the fourth wiring overlaps the semiconductor layer.

11. A semiconductor device comprising:

a first transistor comprising a first gate electrode and a first electrode functions as a source or drain electrode of the first transistor; and

a second transistor comprising second gate electrode and a second electrode functions as a source or drain of the second transistor,

wherein;

the first transistor and the second transistor comprises;

a common oxide semiconductor layer comprising a channel formation region of the first transistor and a channel formation region of the second transistor, wherein an entire bottom surface of the common oxide semiconductor layer is in contact with an insulating surface; and

a common electrode over and in contact with the common oxide semiconductor layer, wherein the common electrode functions as a source or drain electrode of the first transistor and the second transistor and is positioned between the channel formation region of the first transistor and the channel formation region of the second transistor,

the first gate electrode is positioned between the first electrode and the common electrode; and

the second gate electrode is positioned between the second electrode and the common electrode.

12. The semiconductor device according to claim 11, wherein the common oxide semiconductor layer comprises indium, gallium, and zinc.

13. The semiconductor device according to claim 11,

wherein the first transistor comprises a first gate insulating film between the first gate electrode and the common oxide semiconductor layer;

and

wherein the second transistor comprises a second gate insulating film between the second gate electrode and the common oxide semiconductor layer.

14. The semiconductor device according to claim 11, wherein the first transistor and the second transistor comprise a common gate insulating film over and in contact with the common oxide semiconductor layer.

15. The semiconductor device according to claim 11, wherein the first gate electrode and the second gate electrode each face a top surface of the common oxide semiconductor layer and a side surface of the common oxide semiconductor layer.

16. The semiconductor device according to claim 11, wherein the first electrode and the second electrode each face a top surface of the common oxide semiconductor layer and a side surface of the common oxide semiconductor layer.

17. The semiconductor device according to claim 11,

wherein the first gate electrode partly overlaps with the first electrode and the common electrode, and

wherein the second gate electrode partly overlaps the second electrode and the common electrode.

18. The semiconductor device according to claim 11, further comprising:

a first capacitor electrically connected to the first electrode of the first transistor; and

a second capacitor electrically connected to the second electrode of the second transistor.

19. The semiconductor device according to claim 11, further comprising:

a first capacitor comprising the first electrode of the first transistor; and

a second capacitor comprising the second electrode of the second transistor.

20. The semiconductor device according to claim 11, comprising:

a first memory cell comprising the first transistor and a first capacitor electrically connected to the first transistor; and

a second memory cell comprising the second transistor and a second capacitor electrically connected to the second transistor.