Semiconductor device having a gate and method of forming the same

• US 10,446,557 B2
• Filed: 07/07/2016
• Issued: 10/15/2019
• Est. Priority Date: 09/18/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dongjin, Lee, Ji-Eun, Jung, Kyoung-Ho, Yamada, Satoru, Jeong, Moonyoung
• Primary Examiner(s): Smith, Bradley
• Application Number:
  US15/204,805
• Publication Number:
  US 20170084615A1
• Time in Patent Office: 1,195 Days
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/3215 Doping the layers
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.

Claims

1. A method of forming a semiconductor device, comprising:

etching a semiconductor substrate to form a gate trench therein;

forming a gate dielectric on the gate trench of the semiconductor substrate;

forming a first conductive material layer on the gate dielectric;

forming a source material layer on the first conductive material layer, the source material layer comprising a first element;

diffusing the first element into the first conductive material layer by performing a thermal treatment process to form a doped material layer;

removing the source material layer formed on the doped material layer in its entirety from the gate trench; and

forming a second conductive material layer that physically contacts the doped material layer;

wherein the first element included in the source material layer is diffused into the first conductive material layer and is not diffused into the gate dielectric during the thermal treatment process.

2. The method of claim 1, further comprising, after the removing of the source material layer, decreasing a thickness of the doped material layer.

3. The method of claim 1, wherein a doping concentration of the first element in a first portion of the doped material layer is higher than that of the first element in a second portion of the doped material layer;

wherein the first portion is farther away from the gate dielectric than the second portion.

4. The method of claim 1, wherein the gate trench is configured to cross an active region,

wherein the gate dielectric is formed on an inner wall of the gate trench.

5. The method of claim 4, further comprising:

forming a second conductive material layer on the doped material layer; and

etching the second conductive material layer and the doped material layer to form a gate electrode,

wherein;

the first conductive material layer is conformally formed on the gate dielectric;

the second conductive material layer fills the gate trench; and

the gate electrode partially fills the gate trench.

6. The method of claim 5, wherein an upper end portion of the first conductive material layer of the gate electrode is formed at a lower level than an upper end portion of the second conductive material layer of the gate electrode relative to the gate dielectric.

7. The method of claim 1, further comprising:

forming a sacrificial gate on the semiconductor substrate;

forming an interlayer insulating layer on side surfaces of the sacrificial gate; and

removing the sacrificial gate to form a the gate trench,

wherein;

the first conductive material layer is conformally formed on the gate dielectric; and

the second conductive material layer fills the gate trench.

8. A method of forming a semiconductor device, comprising:

etching a semiconductor substrate to form a gate trench therein;

forming a gate dielectric on the gate trench of the semiconductor substrate;

forming a first conductive material layer on the gate dielectric;

forming a source material layer on the first conductive material layer, the source material being separated from the gate dielectric so as not to contact the gate dielectric and comprising a first element;

diffusing the first element into the first conductive material layer by performing a thermal treatment process to form a doped material layer;

removing the source material layer formed on the doped material layer in its entirety from the gate trench; and

forming a second conductive material layer that physically contacts the doped material layer.

9. The method of claim 8, wherein the first conductive material layer has a substantially uniform thickness.

10. The method of claim 9, wherein a work function of the first conductive material layer is higher than a work function of the doped material layer.

11. The method of claim 10, wherein a doping concentration of the first element in a first portion of the doped material layer is higher than that of the first element in a second portion of the doped material layer,

wherein the first portion is farther away from the gate dielectric that the second portion.

12. The method of claim 11, wherein the doped material layer comprises one of WN and TiN;

and

wherein the first element comprises La.