Partially disposed gate layer into the trenches

• US 10,446,563 B1
• Filed: 04/04/2018
• Issued: 10/15/2019
• Est. Priority Date: 04/04/2018
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bo, Xiang-Zheng, Macpeak, John H., Grider, Douglas T.
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US15/945,552
• Publication Number:
  US 20190312045A1
• Time in Patent Office: 559 Days
• CPC Class Codes: G01B 2210/56 Measuring geometric parameters of semiconductor structures, e.g. profile, critical dimensions or trench depth
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND

Abstract

In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.

Claims

1. A method, comprising:

obtaining a wafer including a plurality of floating gate layers;

measuring thicknesses of the plurality of floating gate layers;

calculating a floating gate thickness variation value using the measured floating gate layer thicknesses and a target value;

etching, at least in part based on the floating gate thickness variation value, a plurality of shallow trench isolation structures; and

increasing, based on the floating gate thickness variation value, an oxide etch time of the wafer.

2. The method of claim 1, wherein measuring the thicknesses of the plurality of floating gate layers using a scatterometer.

3. The method of claim 1, wherein, in response to increasing the oxide etch time of the wafer, increasing a wrap-around area of a plurality of word line gate layers in the plurality of shallow trench isolation structures.

4. The method of claim 1 further comprising depositing a plurality of word line gate layers such that the plurality of word line gate layers partially extend into each of the plurality of shallow trench isolation structures.

5. A method, comprising:

obtaining a substrate layer having an outer surface and comprising a plurality of shallow trench isolation structures extending from a first surface above the outer surface into the substrate layer, wherein a first dielectric layer interfaces with the outer surface, and wherein a plurality of floating gate layers are positioned on the first dielectric layer;

measuring a thickness of each of the plurality of floating gate layers;

calculating a floating gate thickness variation value using the measured thicknesses of the plurality of floating gate layers with a target value; and

etching the plurality of shallow trench isolation structures based on the floating gate thickness variation value.

6. The method of claim 5 further comprising increasing etching time of the plurality of shallow isolation structures based on the floating gate thickness variation value.

7. The method of claim 5 further comprising depositing a plurality of gate layers such that the plurality of gate layers partially extend into each of the plurality of shallow trench isolation structures.

8. The method of claim 7 further comprising patterning each of the plurality of gate layers to form a plurality of word line gate layers.

9. The method of claim 5 further comprising depositing the plurality of gate layers based on the measured thicknesses of the plurality of floating gate layers.

10. The method of claim 5 further comprising forming a plurality of active regions between two consecutive shallow trench isolation structures.

11. The method of claim 10, wherein the substrate layer, in each of the plurality of active regions, comprises at least one implant layer.

12. The method of claim 5, wherein the substrate layer comprises silicon, the plurality of floating gate layers comprises polysilicon, and the first dielectric layer comprises silicon dioxide.

13. The method of claim 12, wherein the floating gate thickness variation value includes a mean value of the measured thicknesses.