Nonvolatile memory device
First Claim
1. A three-dimensional (3D) nonvolatile memory comprising:
- a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers, wherein the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, a connection region between the first cell region and the second cell region; and
a hole,wherein the connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region, andwherein the hole is surrounded by the first step portion, the second step portion, and the connection region and exposes a lower region below the stacked structure.
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Accused Products
Abstract
A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.
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Citations
19 Claims
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1. A three-dimensional (3D) nonvolatile memory comprising:
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a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers, wherein the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, a connection region between the first cell region and the second cell region; and a hole, wherein the connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region, and wherein the hole is surrounded by the first step portion, the second step portion, and the connection region and exposes a lower region below the stacked structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A three-dimensional (3D) nonvolatile memory comprising:
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a lower region that includes a lower substrate and a peripheral circuit on the lower substrate; and a stacked structure on the lower region, wherein the stacked structure includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers, wherein the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region, and the connection region of the stacked structure includes a step portion that has a stepped shape that descends from a periphery of the connection region toward a center thereof, wherein at least some of steps of the step portion have an annular rectangular shape. - View Dependent Claims (11, 12, 13, 14)
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15. A three-dimensional (3D) nonvolatile memory comprising:
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a lower region that includes a lower substrate and a peripheral circuit on the lower substrate; an upper substrate on the lower region; a stacked structure on the upper substrate that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers; and a plurality of contacts that electrically connect each of the plurality of conductive layers to the peripheral circuit, wherein the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region, the connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction toward the second cell region, and a connection portion that connects the first step portion and the second cell region, and the plurality of contacts are disposed in the first step portion. - View Dependent Claims (16, 17, 18, 19)
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Specification