Nonvolatile memory device

• US 10,446,575 B2
• Filed: 06/21/2018
• Issued: 10/15/2019
• Est. Priority Date: 11/07/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kim, Chan-Ho, Lim, Bong-Soon, Kwak, Pan-Suk, Jeon, Hong-Soo
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US16/014,902
• Publication Number:
  US 20190139978A1
• Time in Patent Office: 481 Days
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.

Claims

1. A three-dimensional (3D) nonvolatile memory comprising:

a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers, wherein the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, a connection region between the first cell region and the second cell region; and

a hole,

wherein the connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region, and

wherein the hole is surrounded by the first step portion, the second step portion, and the connection region and exposes a lower region below the stacked structure.

2. The 3D nonvolatile memory of claim 1, wherein

one sidewall of the connection portion is aligned with one sidewall of the first cell region and one sidewall of the second cell region.

3. The 3D nonvolatile memory of claim 1, wherein

at least one of steps of the first step portion is at a same level as one of steps of the second step portion.

4. The 3D nonvolatile memory of claim 1, further comprising:

a lower region disposed below the stacked structure and that includes a peripheral circuit, wherein

portions of the plurality of conductive layers disposed in the first cell region and portions of the plurality of conductive layers disposed in the second cell region are electrically connected to the peripheral circuit.

5. The 3D nonvolatile memory of claim 1, wherein

each of the plurality of conductive layers extends over the first cell region, the first step portion, the connection portion, the second step portion, and the second cell region.

6. The 3D nonvolatile memory of claim 1, wherein

at least one step of the first step portion and the second step portion has a plurality of sub steps that have different widths in one direction.

7. The 3D nonvolatile memory of claim 1, wherein

a width of the connection portion in a direction perpendicular to a direction from the first step portion to the second step portion increases with decreasing height from a lower end of the connection portion.

8. The 3D nonvolatile memory of claim 1, wherein

the connection portion includes a third step portion and a fourth step portion, each connecting the first step portion and the second step portion and each having a stepped shape that descends in a direction in which the third step portion and the fourth step portion face each other.

9. The 3D nonvolatile memory of claim 1, wherein

the connection portion connects a lower portion of the first step portion and a lower portion of the second step portion but not an upper portion of the first step portion and an upper portion of the second step portion.

10. A three-dimensional (3D) nonvolatile memory comprising:

a lower region that includes a lower substrate and a peripheral circuit on the lower substrate; and

a stacked structure on the lower region, wherein the stacked structure includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers, wherein

the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region, and

the connection region of the stacked structure includes a step portion that has a stepped shape that descends from a periphery of the connection region toward a center thereof,

wherein at least some of steps of the step portion have an annular rectangular shape.

11. The 3D nonvolatile memory of claim 10, wherein

at least one of the plurality of conductive layers within the stacked structure includes a first portion in the first cell region, a second portion in the second cell region, and a third portion in the connection region that connects the first portion and the second portion.

12. The 3D nonvolatile memory of claim 10, wherein

at least one of the plurality of conductive layers within an upper portion of the stacked structure includes a first portion in the first cell region and a second portion in the second cell region that is spaced apart from the first portion, and the first portion and the second portion are connected to each other through an upper conductive line disposed at a higher level than the stacked structure.

13. The 3D nonvolatile memory of claim 10, wherein

the step portion includes a first step portion, a second step portion, a third step portion and a fourth step portion, wherein the first step portion contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, the second step portion contacts the second cell region and has a stepped shape that descends in a direction toward the first cell region, each of the third step portion and the fourth step portion connects the first step portion and the second step portion and each of the third step portion and the fourth step portion has a stepped shape that descends in a direction toward each other.

14. The 3D nonvolatile memory of claim 13, further comprising:

a plurality of contacts located in the first step portion, the second step portion, the third step portion, and the fourth step portion, wherein plurality of contacts electrically connect the plurality of conductive layers to the peripheral circuit.

15. A three-dimensional (3D) nonvolatile memory comprising:

a lower region that includes a lower substrate and a peripheral circuit on the lower substrate;

an upper substrate on the lower region;

a stacked structure on the upper substrate that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers; and

a plurality of contacts that electrically connect each of the plurality of conductive layers to the peripheral circuit, wherein

the stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region,

the connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction toward the second cell region, and a connection portion that connects the first step portion and the second cell region, and

the plurality of contacts are disposed in the first step portion.

16. The 3D nonvolatile memory of claim 15, wherein the second cell region includes a flat sidewall that faces the first step portion.

17. The 3D nonvolatile memory of claim 15, wherein

each of the plurality of conductive layers extends over the first cell region, the first step portion, the connection portion, and the second cell region.

18. The 3D nonvolatile memory of claim 15, wherein

the connection portion includes a third step portion and a fourth step portion spaced apart from the third step portion, wherein each of the third step portion and the fourth step portion connects the first step portion and the second cell region and has a stepped shape that descends in a direction toward each other.

19. The 3D nonvolatile memory of claim 15, wherein

the connection portion includes two portions spaced apart from each other in a first direction, wherein a width in the first direction of each of the two portions increases with decreasing distance from the lower region, and a distance in the first direction between the two portions decreases with decreasing distance from the lower region.