Display substrate comprising a plurality of conductive patterns

• US 10,446,587 B2
• Filed: 05/12/2017
• Issued: 10/15/2019
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ji-Sun, Kim, Ji-Hyun, Choi, Shin-Il, Kwon, Yeong-Keun
• Primary Examiner(s): Ahmadi, Mohsen
• Assistant Examiner(s): Roland, Christopher M
• Application Number:
  US15/594,325
• Publication Number:
  US 20170250203A1
• Time in Patent Office: 886 Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

A display substrate includes a switching element disposed in a display region that is electrically connected to a gate line, a data line, and a first electrode in a peripheral region adjacent to the display region that includes a first conductive pattern formed from a first conductive layer that includes a same material as the gate line, a first line connecting part disposed in the peripheral region that includes the first conductive pattern, a second conductive pattern that overlaps the first conductive pattern and formed, an organic layer that partially exposes the second conductive pattern, and a third conductive pattern electrically connected to the second conductive pattern that contacts the partially exposed second conductive pattern, and a fourth conductive pattern that electrically connects the first conductive pattern of the pad part and the third conductive pattern of the first line connecting part.

Claims

1. A method of manufacturing a display substrate comprising:

forming a first conductive pattern on a base substrate;

forming a second conductive pattern on the first conductive pattern, wherein the second conductive pattern is formed from a same layer as a source electrode and a drain electrode;

forming an organic layer on the second conductive pattern;

partially removing the organic layer wherein a portion of the second conductive pattern is exposed;

forming a third conductive pattern on the second conductive pattern that covers the portion of the second conductive pattern exposed by the organic layer;

forming a protective layer on the third conductive pattern;

patterning the protective layer wherein a portion of the first conductive pattern is exposed and a portion of the third conductive pattern is exposed; and

forming a fourth conductive pattern in contact with the partially exposed first conductive pattern and the partially exposed third conductive pattern,

wherein the third conductive pattern is formed from a same layer as a first electrode electrically connected to the drain electrode,

wherein a second electrode is disposed on the first electrode and overlaps the first electrode,

wherein the second electrode is separated from the first electrode by the protective layer and the fourth conductive pattern is formed from a same layer as the second electrode.

2. The method of claim 1, wherein the first conductive pattern is formed from a same layer as a gate electrode.

3. The method of claim 1, wherein the second electrode is supplied with a common voltage.