Non-volatile random access memory (NVRAM)

• US 10,446,608 B2
• Filed: 09/30/2014
• Issued: 10/15/2019
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Roy, Anirban
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US14/501,781
• Publication Number:
  US 20160093671A1
• Time in Patent Office: 1,841 Days
• Field of Search: 257 4
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors

Abstract

A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first transistor structure over a substrate;

forming a second transistor structure over the substrate;

forming a capacitor structure in a trench in the substrate between the first and second transistor structures, the capacitor structure comprising;

a heavily doped liner in the trench, the heavily doped liner having the same conductivity type as that of a source/drain portion of the first transistor structure and of a source/drain portion of the second transistor structure, the heavily doped liner electrically coupled to and contiguous with a bottom-most surface of the source/drain of the first transistor structure and contiguous with a bottom-most surface of the source/drain of the second transistor structure;

a dielectric layer adjacent to the heavily doped liner and below the top surface of the substrate; and

a conductive fill material over the dielectric layer in the trench;

forming a first conductive contact from the first transistor structure to a first bit line;

forming a second conductive contact from the second transistor to a first terminal of a non-volatile memory element; and

forming a third conductive contact from a second terminal of the non-volatile memory element to a second bit line used to access the non-volatile memory element,

wherein the non-volatile memory element is in series between the second transistor and the second bit line.

2. The method of claim 1, wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.

3. The method of claim 1, wherein the first conductive contact comprises:

a first via electrically coupled to a source/drain region of the first transistor structure;

a second via electrically coupled to the first bit line; and

a first portion of a first metal layer electrically coupled to the first and second vias.

4. The method of claim 3, wherein the second conductive contact comprises:

a third via electrically coupled to a source/drain region of the second transistor structure;

a fourth via;

a second portion of the first metal layer electrically coupled to the third and fourth vias;

a fifth via; and

a portion of a second metal layer electrically coupled to the fourth and fifth vias.

5. The method of claim 1, wherein the non-volatile memory element comprises a variable resistive element.

6. The method of claim 5, wherein the variable resistive element comprises one of a group consisting of:

a resistive random access memory element, a magnetic random access memory element, a phase-change memory resistive element, and a carbon nanotube resistive element.

7. The method of claim 1, further comprising:

forming a fourth conductive contact from the second transistor to a conductive contact of the capacitor structure, the capacitor structure coupled to the non-volatile memory element via activation of a gate of the second transistor, and wherein the heavily doped liner is below a top surface of the substrate.

8. A method of making a semiconductor device, the method comprising:

forming a first transistor structure over a substrate;

forming a second transistor structure over the substrate;

forming a capacitor structure in a trench in the substrate between the first and second transistor structures, a first plate of the capacitor structure comprising a heavily doped liner in the trench and below a top surface of the substrate, the heavily doped liner having a same conductivity type as that of a source/drain portion of the first transistor structure and of a source/drain portion of the second transistor structure, the heavily doped liner electrically coupled to and contiguous with a bottom-most surface of the source/drain portion of the first transistor structure and coupled to and contiguous with a bottom-most surface of the source/drain portion of the second transistor structure;

forming a first conductive contact from the first transistor structure to a first bit line;

forming a second conductive contact from the second transistor structure to a first terminal of a variable resistive element; and

forming a third conductive contact from a second terminal of the variable resistive element to a second bit line used to access the variable resistive element,

wherein the variable resistive element is in series between the second transistor and the second bit line.

9. The method of claim 8, wherein the capacitor structure further comprises:

a dielectric layer over an inner surface of the heavily doped layer; and

a conductive fill material over an inner surface of the dielectric layer forming a second plate of the capacitor structure.

10. The method of claim 9, wherein the capacitor structure further comprises a conductive cap structure over the conductive fill material.

11. The method of claim 8, wherein the first conductive contact comprises:

a first via electrically coupled to a source/drain region of the first transistor structure;

a second via electrically coupled to the first bit line; and

a first portion of a first metal layer electrically coupled to the first and second vias.

12. The method of claim 11, wherein the second conductive contact comprises:

a third via electrically coupled to a source/drain region of the second transistor structure;

a fourth via;

a second portion of the first metal layer electrically coupled to the third and fourth vias;

a fifth via; and

a portion of a second metal layer electrically coupled to the fourth and fifth vias.

13. The method of claim 8, wherein the variable resistive element comprises one of a group consisting of:

a resistive random access memory element, a magnetic random access memory element, a phase-change memory resistive element, and a carbon nanotube resistive element.