Approach to minimization of strain loss in strained fin field effect transistors

• US 10,446,647 B2
• Filed: 10/23/2017
• Issued: 10/15/2019
• Est. Priority Date: 10/17/2016
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Li, Juntao, Xu, Peng
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US15/790,826
• Publication Number:
  US 20180108771A1
• Time in Patent Office: 722 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

Claims

1. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:

forming a monolithic fin loop on a substrate;

forming a plurality of gate structures across straight portions of the monolithic fin loop;

forming a source/drain on the monolithic fin loop adjacent to each of the plurality of gate structures;

forming an interlevel dielectric on the monolithic fin loop;

removing portions of the interlevel dielectric to form openings down to the each of the source/drains and substrate surface;

forming a source/drain contact to each of the source/drains on opposite sides of each gate structure;

selectively removing one or more, but fewer than all, of the source/drain contacts to form a trench adjacent to a gate structure that exposes underlying source/drains;

removing the exposed source/drains to expose the underlying portions of the monolithic fin loop, and

removing the exposed portions of the monolithic fin loop.

2. The method of claim 1, wherein the monolithic fin loop has an oval or rectangular shape.

3. The method of claim 1, wherein the monolithic fin loop is single crystal silicon-germanium (SiGe) and the substrate is single crystal silicon.

4. The method of claim 1, wherein the source/drain contacts are tungsten, titanium, cobalt, or a combination thereof.

5. The method of claim 1, wherein the source/drain contacts are removed using a selective dry etch.

6. The method of claim 1, wherein each trench is self-aligned with the adjacent gate structure by removal of the source/drain contacts.

7. A method of fabricating a vertical fin field effect transistor with a strained channel, comprising:

forming a strained silicon-germanium (SiGe) vertical fin on a single crystal silicon substrate or a strained silicon (Si) vertical fin on a single crystal silicon-germanium substrate;

forming three or more gate structures on the strained SiGe or Si vertical fin;

forming a gate spacer on each of the three or more gate structures, respectively;

forming a source/drain adjacent to each of the three or more gate spacers, respectively;

forming an interlevel dielectric on the gate spacers and the source/drains;

forming four or more openings in the interlevel dielectric, wherein each of the openings exposes one of the source/drains;

forming four or more source/drain contacts in the interlevel dielectric on the source/drains, wherein at least two of the source/drain contacts are between the gate spacers;

selectively removing one or more, but fewer than all, of the source/drain contacts to form a trench in the interlevel dielectric that exposes the underlying source/drains;

removing the exposed source/drain and an underlying portion of the strained SiGe or Si vertical fin from the one or more trenches to form a plurality of strained SiGe or Si vertical fin sections; and

extending the one or more trenches into the substrate by a predetermined depth.

8. The method of claim 7, wherein the strained silicon-germanium (SiGe) vertical fin is epitaxially grown on the single crystal silicon substrate, or the strained silicon (Si) vertical fin is epitaxially grown on a single crystal silicon-germanium substrate.

9. The method of claim 7, wherein the height of the SiGe vertical fin and the germanium (Ge) concentration of the SiGe vertical fin are below a threshold value at which dislocations would appear in the vertical fin.

10. The method of claim 7, further comprising forming an insulating liner in each of the one or more trenches.

11. A method of forming a vertical fin device, comprising:

forming a plurality of adjacent strained, straight, vertical fin segments on a substrate;

forming a gate spacer on each of the plurality of strained, straight, vertical fin segments;

forming a gate structure within each of the gate spacers;

forming a source/drain contact on each of the plurality of strained, straight, vertical fin segments adjacent to at least one of the plurality of gate spacers;

forming an interlevel dielectric on each gate spacer and the remaining source/drain contacts;

selectively removing one or more, but fewer than all, of the source/drain contacts to form a trench in the interlevel dielectric that exposes an underlying source/drain;

removing the exposed source/drain(s) and an underlying portion of the strained SiGe or Si vertical fin from the one or more trenches to form a plurality of strained SiGe or Si vertical fin sections; and

extending the one or more trenches into the substrate by a predetermined depth.

12. The method of claim 11, wherein the plurality of adjacent strained, straight, vertical fin segments are formed from an oval or rectangular monolithic fin loop, and each gate spacer and gate structure spans two adjacent vertical fin segments formed from the same monolithic fin loop.

13. The method of claim 11, wherein the gate structure includes a gate dielectric, a work function layer, and a conductive gate fill layer.

14. The method of claim 11, further comprising an insulating liner on at least a portion of one of the plurality gate spacers and on the substrate, and a trench fill on the insulating liner.

15. The method of claim 14, wherein the gate spacer has a thickness in the range of about 3 nm to about 15 nm, and the insulating liner has a thickness in the range of about 3 nm to about 15 nm.