Semiconductor device comprising slanted slope electrode contact windows

• US 10,446,661 B2
• Filed: 03/13/2017
• Issued: 10/15/2019
• Est. Priority Date: 04/12/2013
• Status: Active Grant

• Current Assignee: Sumitomo Electric Device Innovations Incorporated (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Device Innovations Incorporated (Sumitomo Corporation)
• Inventors: Nishi, Masahiro
• Primary Examiner(s): Whalen, Daniel
• Application Number:
  US15/457,549
• Publication Number:
  US 20170186851A1
• Time in Patent Office: 946 Days
• Field of Search: None
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.

Claims

1. A semiconductor device comprising:

a semiconductor layer formed on a substrate, the semiconductor layer including an electron transit layer on the substrate, an electron supply layer on the electron transit layer, and a cap layer on the electron supply layer;

an electrode contact window that includes a recess formed in the electron supply layer and the cap layer, the recess providing an inner wall that has a slanted slope, the inner wall exposing the electron supply layer and the cap layer; and

a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer,

wherein the recess includes an edge at a surface of the cap layer and a bottom in the electron supply layer but apart from the electron transit layer, the slanted slope extending from the bottom to the edge of the recess, and

wherein the drain electrode is formed in the recess.

2. The semiconductor device according to claim 1,

wherein the slanted slope traverses the cap layer, and

wherein the drain electrode extends to the cap layer exposed on the slanted slope.

3. The semiconductor device according to claim 2,

wherein the semiconductor layer has a top surface where the drain electrode extends thereon.

4. The semiconductor device according to claim 1,

wherein the semiconductor layer includes a nitride semiconductor layer.

5. The semiconductor device according to claim 4,

wherein the electron supply layer includes AlGaN or InAlN, and the cap layer includes GaN.

6. The semiconductor device according to claim 1,

wherein the slanted slope has a width along a direction horizontal to a surface of the substrate that is equal to or greater than 0.03 μ

m but equal to or smaller than 0.1 μ

m.

7. The semiconductor device according to claim 1,

wherein the semiconductor layer includes a doping region containing dopant, and

wherein the recess is formed in the doping region.

8. The semiconductor device according to claim 1, further comprising a passivation layer that covers a top surface of the semiconductor layer between the source electrode and the drain electrode, the slanted slope within the electrode contact window, the source electrode, and the drain electrode, the passivation layer having an opening between the source electrode and the drain electrode and exposing the top surface of the semiconductor layer,

wherein the gate electrode is provided within the opening of the passivation layer to be in direct contact with the semiconductor layer.

9. A semiconductor device comprising:

a semiconductor layer formed on a substrate, the semiconductor layer including an electron transit layer on the substrate, an electron supply layer on the electron transit layer, and a cap layer on the electron supply layer, the semiconductor layer having a top surface;

an electrode contact window that includes a recess formed in the electron supply layer and the cap layer, the recess providing an inner wall having a slanted slope and a bottom that is located in the electron supply layer but apart from the electron transit layer, the slanted slope extending from the bottom to the top surface of the semiconductor layer; and

a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer,

wherein the drain electrode is provided in the recess.

10. The semiconductor device according to claim 9,

wherein the slanted slope traverses the cap layer, and

wherein the drain electrode extends to the cap layer exposed on the slanted slope.

11. The semiconductor device according to claim 9,

wherein the semiconductor layer includes a nitride semiconductor layer.

12. The semiconductor device according to claim 11,

wherein the electron supply layer includes AlGaN or InAlN, and the cap layer includes GaN.

13. The semiconductor device according to claim 9,

wherein the slanted slope has a width along a direction horizontal to a surface of the substrate that is equal to or greater than 0.03 μ

m but equal to or smaller than 0.1 μ

m.

14. The semiconductor device according to claim 9,

wherein the semiconductor layer includes a doping region containing dopant, and

wherein the recess is formed in the doping region.

15. The semiconductor device according to claim 9, further comprising a passivation layer that covers a top surface of the semiconductor layer between the source electrode and the drain electrode, the slanted slope within the electrode contact window, the source electrode, and the drain electrode, the passivation layer having an opening between the source electrode and the drain electrode and exposing the top surface of the semiconductor layer,

wherein the gate electrode is provided within the opening of the passivation layer to be in direct contact with the semiconductor layer.