Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

• US 10,446,662 B2
• Filed: 01/31/2017
• Issued: 10/15/2019
• Est. Priority Date: 10/07/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Bih, Shih Wei, Liao, Han-Wen, Yan, Xuan-You, Chen, Yen-Yu, Lin, Chun-Chih
• Primary Examiner(s): Trinh, Michael M
• Application Number:
  US15/420,580
• Publication Number:
  US 20180102418A1
• Time in Patent Office: 987 Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a polysilicon layer over a substrate;

etching the polysilicon layer to form a dummy gate electrode having a top portion with a first lateral dimension, a middle portion with a second lateral dimension, and a bottom portion with a third lateral dimension, the first lateral dimension being greater than the second lateral dimension, and the second lateral dimension being greater than the third lateral dimension wherein the etching is performed using at least three etching steps and by increasing a fluorine content of an etchant for each step of the at least three etching steps; and

replacing the dummy gate electrode with a metal gate electrode.

2. The method of claim 1, further comprising:

before the forming of the polysilicon layer, forming a high-k gate dielectric layer over the substrate, wherein the polysilicon layer is formed over the high-k gate dielectric layer.

3. The method of claim 1, further comprising, before the replacing of the dummy gate electrode:

forming spacers on sidewalls of the dummy gate electrode;

forming source/drain regions in the substrate on opposite sides of the dummy gate electrode; and

forming an interlayer dielectric (ILD) over the substrate.

4. The method of claim 1, wherein:

the top portion of the dummy gate electrode is formed when the etching is performed with a first lateral etching rate;

the middle portion of the dummy gate electrode is formed when the etching is performed with a second lateral etching rate greater than the first lateral etching rate; and

the bottom portion of the dummy gate electrode is formed when the etching is performed with a third lateral etching rate greater than the second lateral etching rate.

5. The method of claim 1, wherein the etching comprises using a fluorine-containing etchant, and wherein the etching is performed by continuously increasing a fluorine content of the etchant as the etching progresses deeper into the polysilicon layer.

6. The method of claim 5, wherein the increasing the fluorine content comprises increasing a flow rate of the fluorine-containing etchant.

7. The method of claim 6, wherein the flow rate is in a range between about 80 sccm and about 120 sccm.

8. The method of claim 5, wherein the etching comprises applying a chorine-containing etchant simultaneously with the fluorine-containing etchant.

9. The method of claim 1, wherein the etching is performed such that the dummy gate electrode has a cross-sectional profile that resembles an upside-down trapezoid.

10. The method of claim 1, wherein the first lateral dimension is greater than the third lateral dimension by at least 20%.

11. The method of claim 1, wherein the etching comprises applying a passivation gas when the top portion of the dummy gate electrode is etched such that a passivation layer is formed on the top portion of the dummy gate electrode but not on the bottom portion of the dummy gate electrode.

12. A method of fabricating a semiconductor device, the method comprising:

forming a gate dielectric layer over a substrate;

forming a dummy gate electrode layer over the gate dielectric layer;

etching, through at least three etching steps, the dummy gate electrode layer with an etchant that contains fluorine and chlorine to form a dummy gate electrode, wherein the etching comprising increasing a fluorine content of the etchant at each etching step as the etching progresses deeper into the dummy gate electrode layer that that a topmost portion of the dummy gate electrode has a maximum width, and that a bottommost portion of the dummy gate electrode has a minimum width;

forming spacers on sidewalls of the dummy gate electrode;

forming source/drain regions in the substrate on opposite sides of the dummy gate electrode; and

replacing the dummy gate electrode with a metal gate electrode.

13. The method of claim 12, wherein the etching is performed such that the dummy gate electrode has a cross-sectional profile that resembles an upside-down trapezoid.

14. The method of claim 12, wherein:

the increasing the fluorine content comprises increasing a flow rate of the etchant that contains fluorine.

15. The method of claim 12, wherein the etching further comprises applying a passivation gas when a top portion of the dummy gate electrode is formed but not when a bottom portion of the dummy gate electrode is formed.

16. The method of claim 12, wherein the etching is performed such that a width of the dummy gate electrode decreases as a depth of the dummy gate electrode increases.

17. A method of fabricating a semiconductor device, comprising:

forming a dummy gate electrode layer over a substrate;

performing a first etching step with a fluorine-containing etchant having a first flow rate to form a top portion of a dummy gate electrode having a first lateral dimension;

performing a second etching step with the fluorine-containing etchant having a second flow rate to form a middle portion of the dummy gate electrode having a second lateral dimension, wherein the second flow rate is greater than the first flow rate, and wherein the second lateral dimension is less than the first lateral dimension;

performing a third etching step with the fluorine-containing etchant having a third flow rate to form a bottom portion of the dummy gate electrode having a third lateral dimension, wherein the third flow rate is greater than the second flow rate, and wherein the third lateral dimension is less than the second lateral dimension; and

replacing the dummy gate electrode with a metal gate electrode.

18. The method of claim 17, further comprising, before the second etching step is performed, applying a passivation gas to form a passivation material on at least the top portion of the dummy gate electrode.

19. The method of claim 17, wherein the first, second, and third etching steps each comprises applying a chlorine-containing etchant, wherein the chlorine-containing etchant and the fluorine-containing etchant are applied simultaneously in each of the first, second, and third etching steps.

20. The method of claim 17, wherein the first, second, and third etching steps are performed using a C_xF_y material as the fluorine-containing etchant, wherein x and y are positive integers.