Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode
First Claim
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1. A method of fabricating a semiconductor device, the method comprising:
- forming a polysilicon layer over a substrate;
etching the polysilicon layer to form a dummy gate electrode having a top portion with a first lateral dimension, a middle portion with a second lateral dimension, and a bottom portion with a third lateral dimension, the first lateral dimension being greater than the second lateral dimension, and the second lateral dimension being greater than the third lateral dimension wherein the etching is performed using at least three etching steps and by increasing a fluorine content of an etchant for each step of the at least three etching steps; and
replacing the dummy gate electrode with a metal gate electrode.
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Abstract
A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
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Citations
20 Claims
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1. A method of fabricating a semiconductor device, the method comprising:
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forming a polysilicon layer over a substrate; etching the polysilicon layer to form a dummy gate electrode having a top portion with a first lateral dimension, a middle portion with a second lateral dimension, and a bottom portion with a third lateral dimension, the first lateral dimension being greater than the second lateral dimension, and the second lateral dimension being greater than the third lateral dimension wherein the etching is performed using at least three etching steps and by increasing a fluorine content of an etchant for each step of the at least three etching steps; and replacing the dummy gate electrode with a metal gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of fabricating a semiconductor device, the method comprising:
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forming a gate dielectric layer over a substrate; forming a dummy gate electrode layer over the gate dielectric layer; etching, through at least three etching steps, the dummy gate electrode layer with an etchant that contains fluorine and chlorine to form a dummy gate electrode, wherein the etching comprising increasing a fluorine content of the etchant at each etching step as the etching progresses deeper into the dummy gate electrode layer that that a topmost portion of the dummy gate electrode has a maximum width, and that a bottommost portion of the dummy gate electrode has a minimum width; forming spacers on sidewalls of the dummy gate electrode; forming source/drain regions in the substrate on opposite sides of the dummy gate electrode; and replacing the dummy gate electrode with a metal gate electrode. - View Dependent Claims (13, 14, 15, 16)
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17. A method of fabricating a semiconductor device, comprising:
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forming a dummy gate electrode layer over a substrate; performing a first etching step with a fluorine-containing etchant having a first flow rate to form a top portion of a dummy gate electrode having a first lateral dimension; performing a second etching step with the fluorine-containing etchant having a second flow rate to form a middle portion of the dummy gate electrode having a second lateral dimension, wherein the second flow rate is greater than the first flow rate, and wherein the second lateral dimension is less than the first lateral dimension; performing a third etching step with the fluorine-containing etchant having a third flow rate to form a bottom portion of the dummy gate electrode having a third lateral dimension, wherein the third flow rate is greater than the second flow rate, and wherein the third lateral dimension is less than the second lateral dimension; and replacing the dummy gate electrode with a metal gate electrode. - View Dependent Claims (18, 19, 20)
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Specification