Trench IGBT with waved floating P-well electron injection

• US 10,446,674 B2
• Filed: 08/28/2017
• Issued: 10/15/2019
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Littelfuse Incorporated
• Original Assignee: Littelfuse Incorporated
• Inventors: Seok, Kyoung Wook
• Primary Examiner(s): Swanson, Walter H
• Assistant Examiner(s): Ly, Kien C
• Application Number:
  US15/687,545
• Publication Number:
  US 20170358669A1
• Time in Patent Office: 778 Days
• Field of Search: None
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a novel waved contour so that it has thinner portions and thicker portions. When the IGBT is on, electrons flow from an N+ emitter, vertically through a channel along a trench sidewall, and to an N− type drift layer. Additional electrons flow through the channel but then pass under the trench, through the floating P well to the floating N+ well, and laterally through the floating N+ well. NPN transistors are located at thinner portions of the floating P type well. The NPN transistors inject electrons from the floating N+ type well down into the N− drift layer. The extra electron injection reduces V_CE(SAT). The waved contour can be made without adding any masking step to an IGBT manufacturing process.

Claims

1. A method of manufacturing a trench Insulated Gate Bipolar Transistor (IGBT) die structure, wherein the trench IGBT die structure has a substantially planar upper semiconductor surface, the method comprising:

forming a floating P type well region that extends into an N−

type drift layer, wherein the floating P type well region has a thinner portion disposed between two of a plurality of thicker portions, wherein the thinner portion of the floating P type well region extends to a depth DP2THIN measured from the substantially planar upper semiconductor surface, wherein the thicker portions of the floating P type well region extend to a depth DP2THICK measured from the substantially planar upper semiconductor surface, wherein DP2THIN is smaller than DP2THICK, wherein the floating P type well region has a closed polygonal outer periphery when the trench IGBT die structure is considered from a top-down perspective, and wherein the floating P type well region at a location along its polygonal outer periphery defines a sidewall of a trench and extends from the substantially planar upper semiconductor surface to the depth DP2THICK, the trench completely surrounding the floating P type well region, wherein the thinner portion of the floating P type well has a polygonal shape when the trench IGBT die structure is considered from the top-down perspective.

2. The method of manufacturing of claim 1, wherein the thinner portion of the floating P type well region is less than half as thick as the thicker portions of the floating P type well region, the method further comprising:

forming a floating N+ type well region that extends into the floating P type well region from the substantially planar upper semiconductor surface, wherein the floating P type well region does not reach the substantially planar upper semiconductor surface but rather the floating N+ type well region is disposed between the floating P type well region and the substantially planar upper semiconductor surface.

3. The method of manufacturing of claim 2, further comprising:

using a mask to define a floating P type ring in an edge termination area of the trench IGBT die structure, wherein the mask is also used to define the thinner portion of the floating P type well region.

4. The method of manufacturing of claim 1, further comprising:

forming the trench between the floating P type well region and a P type body region, wherein the floating P type well region is formed such that in an IGBT on state at least some electrons are injected from the floating P type well region down into the N−

type drift layer at locations none of which is disposed under the trench and none of which is disposed under the P type body region.

5. The method of manufacturing of claim 1, further comprising:

forming a floating N+ type well region that extends into the floating P type well region from the substantially planar upper semiconductor surface, wherein the floating N+ type well region extends over the thinner portion.

6. The method of manufacturing of claim 1, wherein the quantity DP2THIN is less than half the quantity DP2THICK.

7. A method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) die structure, the method comprising:

forming a floating P type well region that extends into an N−

type drift layer and that is laterally separated from a P type body region, wherein the N−

type drift layer is disposed over a P type collector layer, wherein the P type body region extends into the N−

type drift layer, wherein the floating P type well region and has at least one thinner portion disposed between two of a plurality of thicker portions, wherein the thinner portion of the floating P type well region extends to a depth DP2THIN measured from a substantially planar upper semiconductor surface, wherein the thicker portions of the floating P type well region extend to a depth DP2THICK measured from the substantially planar upper semiconductor surface, wherein DP2THIN is smaller than DP2THICK, wherein the floating P type well region has a closed polygonal outer periphery when the trench IGBT die structure is considered from a top-down perspective, and wherein the floating P type well region at a location along its polygonal outer periphery defines a sidewall of a trench and extends from the substantially planar upper semiconductor surface to the depth DP2THICK, the trench completely surrounding the floating P type well region;

forming a trench gate electrode disposed in the trench, wherein the trench gate electrode is disposed at least in part between the P type body region on one side of the trench and the floating P type well region on an opposite side of the trench; and

forming a floating N+ type well region that extends into the floating P type well region from a substantially planar upper semiconductor surface, wherein the floating P type well region is separated from the substantially planar upper semiconductor surface by the floating N+ type well region, and wherein the floating N+ type well region extends laterally over the at least one thinner portion, wherein the trench extends from the substantially planar upper semiconductor surface to a depth DT, wherein the P type body region extends to a depth DP1 measured from the substantially planar upper semiconductor surface, wherein the thicker portions of the floating P type well region extend to a depth DP2THICK measured from the substantially planar upper semiconductor surface, wherein DT is greater than DP1, and wherein DT is greater than DP2THICK, wherein the floating N+ type well region has a polygonal outer periphery when the IGBT die structure is considered from a top-down perspective, and wherein the trench extends around the outer periphery of the floating N+ type well region and the floating P type well region such that it surrounds the floating N+ type well region and the floating P type well region when the IGBT die structure is considered from the top-down perspective.

8. The method of manufacturing of claim 7, further comprising:

forming an N+ type emitter region that extends into the P type body region from the substantially planar upper semiconductor surface.

9. The method of manufacturing of claim 7, further comprising:

using a mask to define a floating P type ring in an edge termination area of the IGBT die structure, wherein the mask is also used to define the at least one thinner portion of the floating P type well region.

10. The method of manufacturing of claim 7, wherein an N+ type buffer layer disposed between the P type collector layer and the N−

type drift layer.

11. The method of manufacturing of claim 7, wherein the at least one thinner portion of the floating P type well region is less than half as thick as each of the thicker portions of the floating P type well region.

12. The method of manufacturing of claim 11, wherein the at least one thinner portion of the floating P type well region has a substantially polygonal shape when the IGBT die structure is considered from a top-down perspective.

13. The method of manufacturing of claim 11, wherein a second thinner portion of the floating P type well region has a substantially polygonal shape when the IGBT die structure is considered from the top-down perspective, and wherein the second thinner portion loops around the at least one thinner portion such that the at least one thinner portion and the second thinner portion are concentric polygons when considered from the top-down perspective of the IGBT die structure.

14. The method of manufacturing of claim 7, wherein the floating P type well region at a location along the trench extends to the depth DP2THICK.

15. The method of manufacturing of claim 7, wherein the polygonal outer periphery of the floating P type well region has a shape taken from the group consisting of:

an octagon, a square with rounded corners, a rectangle, a rectangle with rounded corners, and a rectangular strip.

16. The method of manufacturing of claim 7, further comprising:

forming an N+ type emitter region that extends into the P type body region from the substantially planar upper semiconductor surface, wherein the N+ type emitter region forms a sidewall of the trench.

17. A method of manufacturing a trench Insulated Gate Bipolar Transistor (IGBT) die structure, wherein the trench IGBT die structure has a substantially planar upper semiconductor surface, the method comprising:

forming a floating P type well region that extends into an N−

type drift layer, wherein the floating P type well region has a thinner portion disposed between two of a plurality of thicker portions, wherein the thinner portion of the floating P type well region extends to a depth DP2THIN measured from the substantially planar upper semiconductor surface, wherein the thicker portions of the floating P type well region extend to a depth DP2THICK measured from the substantially planar upper semiconductor surface, wherein DP2THIN is smaller than DP2THICK, wherein the floating P type well region has a closed polygonal outer periphery when the trench IGBT die structure is considered from a top-down perspective, and wherein the floating P type well region at all locations along its polygonal outer periphery defines a sidewall of a trench and extends from the substantially planar upper semiconductor surface to the depth DP2THICK, the trench completely surrounding the floating P type well region, wherein the thinner portion of the floating P type well region is less than half as thick as the thicker portions of the floating P type well region, the method further comprising;

forming a floating N+ type well region that extends into the floating P type well region from the substantially planar upper semiconductor surface, wherein the floating P type well region does not reach the substantially planar upper semiconductor surface but rather the floating N+ type well region is disposed between the floating P type well region and the substantially planar upper semiconductor surface.

18. The method of manufacturing of claim 17, further comprising:

using a mask to define a floating P type ring in an edge termination area of the trench IGBT die structure, wherein the mask is also used to define the thinner portion of the floating P type well region.