Semiconductor structures and method for fabricating the same

• US 10,446,677 B2
• Filed: 03/16/2018
• Issued: 10/15/2019
• Est. Priority Date: 03/16/2018
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Hebert, Francois
• Primary Examiner(s): Mazumder, Didarul A
• Application Number:
  US15/923,134
• Publication Number:
  US 20190288099A1
• Time in Patent Office: 578 Days
• Field of Search: 257 76
• CPC Class Codes: H01L 21/02002 Preparing wafers
• CPC Class Codes: H01L 21/02376 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/2654 in AIIIBV compounds
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/3731 Ceramic materials or glass H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3732 Diamonds
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0843 : Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1075 : of field-effect transistors
• CPC Class Codes: H01L 29/2003 : Nitride compounds
• CPC Class Codes: H01L 29/205 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 : with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor structure is provided. The semiconductor structure includes an insulating substrate including a first region and a second region; an engineered layer surrounding the insulating substrate; a nucleation layer formed on the engineered layer; a buffer layer formed on the nucleation layer; a first epitaxial layer formed on the buffer layer; a second epitaxial layer formed on the first epitaxial layer; an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer and the nucleation layer, and located between the first region and the second region; a first gate, a first source and a first drain formed on the second epitaxial layer within the first region; and a second gate, a second source, and a second drain formed on the second epitaxial layer within the second region.

Claims

1. A semiconductor structure, comprising:

an insulating substrate comprising a first region and a second region;

an engineered layer surrounding the insulating substrate;

a nucleation layer formed on the engineered layer;

a buffer layer formed on the nucleation layer;

a first epitaxial layer formed on the buffer layer;

a second epitaxial layer formed on the first epitaxial layer;

an isolation structure at least formed in the second epitaxial layer, the first epitaxial layer, the buffer layer and the nucleation layer, and located between the first region and the second region;

a first gate formed on the second epitaxial layer within the first region;

a first source and a first drain formed on the second epitaxial layer within the first region, wherein the first source and the first drain are located on both sides of the first gate;

a second gate formed on the second epitaxial layer within the second region; and

a second source and a second drain formed on the second epitaxial layer within the second region, wherein the second source and the second drain are located on both sides of the second gate.

2. The semiconductor structure as claimed in claim 1, wherein the insulating substrate has a coefficient of thermal expansion (CTE) that is similar to that of the first epitaxial layer.

3. The semiconductor structure as claimed in claim 1, wherein the insulating substrate has a bulk resistivity that is greater than 10⁶ ohm-cm.

4. The semiconductor structure as claimed in claim 1, wherein the insulating substrate has a thermal conductivity that is higher than that of silicon.

5. The semiconductor structure as claimed in claim 1, wherein the insulating substrate comprises aluminum nitride, polycrystalline silicon carbide, polycrystalline diamond, or a mixture thereof.

6. The semiconductor structure as claimed in claim 1, wherein the engineered layer comprises nitride, oxide, oxynitride or polysilicon.

7. The semiconductor structure as claimed in claim 1, wherein the nucleation layer comprises silicon <

111>

.

8. The semiconductor structure as claimed in claim 1, wherein the nucleation layer is crystalline.

9. The semiconductor structure as claimed in claim 1, wherein the nucleation layer has a thickness that is in a range from about 0.1 μ

m to about 5 μ

m.

10. The semiconductor structure as claimed in claim 1, wherein the buffer layer comprises aluminum gallium nitride or aluminum nitride.

11. The semiconductor structure as claimed in claim 1, wherein the first epitaxial layer comprises gallium nitride.

12. The semiconductor structure as claimed in claim 1, wherein the second epitaxial layer comprises aluminum gallium nitride.

13. The semiconductor structure as claimed in claim 1, wherein the isolation structure comprises a trench filled with an insulating material passing through the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer.

14. The semiconductor structure as claimed in claim 1, wherein the isolation structure comprises a trench filled with an insulating material passing through the second epitaxial layer, the first epitaxial layer, the buffer layer, the nucleation layer, and a portion of the engineered layer.

15. The semiconductor structure as claimed in claim 13, wherein the insulating material comprises oxide, nitride followed by oxide, or oxide followed by polysilicon.

16. The semiconductor structure as claimed in claim 1, wherein the isolation structure comprises a first implant region and a second implant region.

17. The semiconductor structure as claimed in claim 16, wherein the first implant region is located in the second epitaxial layer and the first epitaxial layer.

18. The semiconductor structure as claimed in claim 16, wherein the second implant region is located in the nucleation layer.

19. The semiconductor structure as claimed in claim 1, wherein the isolation structure comprises a continuous implant region covering sides of the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer.

20. The semiconductor structure as claimed in claim 1, wherein the first gate, the first source, and the first drain constitute a high-voltage device.

21. The semiconductor structure as claimed in claim 1, wherein the second gate, the second source, and the second drain constitute a low-voltage device or a high-voltage device.

22. The semiconductor structure as claimed in claim 1, further comprising a third epitaxial layer formed on the second epitaxial layer.

23. The semiconductor structure as claimed in claim 22, wherein the third epitaxial layer is a p-type gallium nitride layer.

24. A method for fabricating a semiconductor structure, comprising:

providing an insulating substrate comprising a first region and a second region with an engineered layer surrounding the insulating substrate;

forming a nucleation layer on the engineered layer;

forming a buffer layer on the nucleation layer;

forming a first epitaxial layer on the buffer layer;

forming a second epitaxial layer on the first epitaxial layer;

forming an isolation structure at least in the second epitaxial layer, the first epitaxial layer, the buffer layer and the nucleation layer, and located between the first region and the second region;

forming a first gate on the second epitaxial layer within the first region;

forming a first source and a first drain on the second epitaxial layer within the first region, wherein the first source and the first drain are located on both sides of the first gate;

forming a second gate on the second epitaxial layer within the second region; and

forming a second source and a second drain on the second epitaxial layer within the second region, wherein the second source and the second drain are located on both sides of the second gate.

25. The method for fabricating a semiconductor structure as claimed in claim 24, wherein the isolation structure is formed by etching a trench passing through the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer, and filling an insulating material into the trench.

26. The method for fabricating a semiconductor structure as claimed in claim 24, wherein the isolation structure is formed by etching a trench passing through the second epitaxial layer, the first epitaxial layer, the buffer layer, the nucleation layer, and a portion of the engineered layer, and filling an insulating material into the trench.

27. The method for fabricating a semiconductor structure as claimed in claim 24, wherein the isolation structure is formed by performing a first implantation on the second epitaxial layer and the first epitaxial layer.

28. The method for fabricating a semiconductor structure as claimed in claim 27, wherein the isolation structure is formed by further performing a second implantation on the nucleation layer.

29. The method for fabricating a semiconductor structure as claimed in claim 24, wherein the isolation structure is formed by performing an implantation on the second epitaxial layer, the first epitaxial layer, the buffer layer, and the nucleation layer.