Thin film transistor array substrate and method for manufacturing the same

• US 10,446,711 B2
• Filed: 06/19/2018
• Issued: 10/15/2019
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Jeon, Jinchae, Cho, Kisul
• Primary Examiner(s): Fan, Bo
• Application Number:
  US16/012,346
• Publication Number:
  US 20180315885A1
• Time in Patent Office: 483 Days
• Field of Search: 349141, 349 43, 345 76, 313483, 257 13, 257 43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

A thin film transistor array substrate and a method for manufacturing the same are disclosed. The thin film transistor array substrate includes a plurality of pixel units defined by a cross structure of gate lines with data lines and power lines on a substrate. Each of the pixel units includes a driving unit, which includes a switching thin film transistor and a driving thin film transistor receiving a signal from the gate line, the data line, and the power line, and a capacitor storing a signal; and a light emitting unit emitting light on a pixel electrode receiving a driving current from the driving thin film transistor. Each of a plurality of shielding patterns is positioned under the switching thin film transistor and the driving thin film transistor of the pixel unit.

Claims

1. A thin film transistor array substrate comprising:

a plurality of pixel units defined by a cross structure of gate lines with data lines and power lines on a substrate, each of the plurality of pixel units including;

a driving unit, which includes a switching thin film transistor and a driving thin film transistor receiving a signal from the gate line, the data line, and the power line, and a capacitor storing a signal; and

a light emitting unit emitting light on a pixel electrode receiving a driving current from the driving thin film transistor; and

a plurality of shielding patterns, each of which is positioned under the switching thin film transistor and the driving thin film transistor of each pixel unit;

wherein the shielding pattern of one pixel unit is connected to the shielding patterns of other pixel units adjacent to the one pixel unit through shielding lines, and

wherein the switching thin film transistor and the driving thin film transistor each have a bottom gate structure, and the shielding line is positioned to overlap at least one of the data line and the power line.

2. The thin film transistor array substrate of claim 1, wherein the switching thin film transistor and the driving thin film transistor each include an etch stopper.

3. A method for manufacturing a thin film transistor array substrate comprising:

forming a shielding pattern on a substrate, on which a plurality of pixel units each including a driving unit and a light emitting unit are to be defined;

forming gate lines, data lines, power lines, a capacitor storing a signal, a switching thin film transistor and a driving thin film transistor, wherein the switching thin film transistor and the driving thin film transistor each includes an active layer, a gate electrode, a source electrode, and a drain electrode, on the substrate, on which the shielding pattern is formed and overlaps with the capacitor, the switching thin film transistor and the driving thin film transistor; and

forming a pixel electrode connected to the driving thin film transistor,

wherein the shielding pattern is formed under the switching thin film transistor and the driving thin film transistor, and

wherein the shielding pattern of one pixel unit is connected to the shielding patterns of other pixel units adjacent to the one pixel unit through shielding lines that are parallel with and overlap with the power lines.

4. The method of claim 3, wherein the shielding lines are connected to a constant voltage driver around an active area of the thin film transistor.

5. The method of claim 3, wherein the switching thin film transistor and the driving thin film transistor each have a top gate structure, and the shielding line is positioned to overlap at least the power line.

6. The method of claim 3, wherein the switching thin film transistor and the driving thin film transistor each have a bottom gate structure, and the shielding line is positioned to overlap at least the power line.

7. The method of claim 6, wherein the switching thin film transistor and the driving thin film transistor each include an etch stopper.

8. The method of claim 3, wherein each of the switching thin film transistor and the driving thin film transistor is formed on a buffer layer positioned on the substrate, and the shielding pattern is positioned between the substrate and the buffer layer.

9. The method of claim 4, wherein a constant voltage from the constant voltage driver is applied to the shielding pattern through the shielding line.

10. The method of claim 3, wherein the shielding pattern has a single layer or a multiple layer.

11. The method of claim 3, wherein the active layer contains oxide and after forming the active layer, the active layer is dehydrated from hydrogen and/or hydroxide ions by a thermal process performed at about 300°

C. to 800°

C.

12. The method of claim 3, wherein the shielding pattern is formed with an opening that entirely exposes the light emitting unit.